Intel® Quark™ SoC X1000
Datasheet
August 2015
Document Number: 329676-005US
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Contents—Intel® Quark™ SoC X1000
Contents
1.0
Introduction ............................................................................................................ 37
1.1
About This Manual ............................................................................................. 37
1.2
Component Overview......................................................................................... 37
1.2.1 SoC CPU Core Features ........................................................................... 38
1.2.2 System Memory Controller Features.......................................................... 39
1.2.3 Embedded SRAM Features ....................................................................... 39
1.2.4 Power Management Features ................................................................... 39
1.2.5 Security Features ................................................................................... 39
1.2.6 PCI Express* Features ............................................................................ 39
1.2.7 Ethernet Features................................................................................... 40
1.2.8 USB2 Host Controller Features ................................................................. 40
1.2.9 USB2 Device Controller Features .............................................................. 40
1.2.10 SD/SDIO/eMMC Controller Features .......................................................... 40
1.2.11 I2C* Master Controller ............................................................................ 40
1.2.12 GPIO Features ....................................................................................... 41
1.2.13 SPI Master Controller .............................................................................. 41
1.2.14 High Speed UART Controller with DMA ...................................................... 41
1.2.15 Legacy Bridge ........................................................................................ 41
1.2.16 Package ................................................................................................ 41
1.3
Component Identification ................................................................................... 41
2.0
Physical Interfaces .................................................................................................. 45
2.1
Pin States Through Reset ................................................................................... 47
2.2
System Memory Signals ..................................................................................... 47
2.3
PCI Express* 2.0 Signals .................................................................................... 48
2.4
Ethernet Interface Signals .................................................................................. 49
2.5
USB 2.0 Interface Signals................................................................................... 49
2.6
Integrated Clock Interface Signals ....................................................................... 50
2.7
SDIO/SD/MMC Signals ....................................................................................... 50
2.8
High Speed UART Interface Signals...................................................................... 51
2.9
I2C* Interface Signals........................................................................................ 51
2.10 Legacy Serial Peripheral Interface (SPI) Signals..................................................... 52
2.11 Serial Peripheral Interface (SPI) .......................................................................... 52
2.12 Real Time Clock (RTC) Interface Signals ............................................................... 53
2.13 Power Management Signals ................................................................................ 53
2.14 JTAG and Debug Interface Signals ....................................................................... 53
2.15 Legacy Interface Signals .................................................................................... 54
2.16 General Purpose I/O Interface Signals.................................................................. 54
2.17 Power And Ground Pins ...................................................................................... 55
2.18 Hardware Straps ............................................................................................... 56
3.0
Ballout and Package Information............................................................................. 59
3.1
Package Diagram .............................................................................................. 59
3.2
Ball Listings ...................................................................................................... 60
4.0
Electrical Characteristics ......................................................................................... 69
4.1
Absolute Maximum Ratings ................................................................................. 69
4.2
Recommended Power Supply Ranges ................................................................... 70
4.3
Maximum Supply Current ................................................................................... 71
4.4
Configurable IO Characteristics ........................................................................... 72
4.5
RTC DC Characteristics....................................................................................... 74
4.6
PCI Express* 2.0 DC/AC Characteristics ............................................................... 74
4.7
USB 2.0 DC/AC Characteristics............................................................................ 77
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4.8
4.9
General Interface Timing ....................................................................................79
4.8.1 Legacy SPI Interface Timing .....................................................................79
4.8.2 SPI0/1 Interface Timing...........................................................................80
4.8.3 SDIO Interface Timing.............................................................................81
Clock AC Timing ................................................................................................82
4.9.1 Reference Clock AC Characteristics............................................................82
5.0
Register Access Methods.........................................................................................85
5.1
Fixed I/O Register Access ...................................................................................85
5.2
Fixed Memory Mapped Register Access .................................................................85
5.3
I/O Referenced Register Access ...........................................................................85
5.4
Memory Referenced Register Access.....................................................................86
5.5
PCI Configuration Register Access ........................................................................86
5.5.1 PCI Configuration Access - CAM: I/O Indexed Scheme .................................86
5.5.2 PCI Configuration Access - ECAM: Memory Mapped Scheme .........................87
5.6
Message Bus Register Access ..............................................................................88
5.7
Register Field Access Types.................................................................................89
6.0
Mapping Address Spaces..........................................................................................91
6.1
Physical Address Space Mappings.........................................................................91
6.1.1 Bridge Memory Map ................................................................................91
6.1.1.1 MMIO ......................................................................................93
6.1.1.2 DOS DRAM ...............................................................................94
6.1.1.3 Additional Mappings...................................................................94
6.1.2 MMIO Map .............................................................................................95
6.2
I/O Address Space .............................................................................................95
6.2.1 Host Bridge I/O Map................................................................................96
6.2.2 I/O Fabric I/O Map..................................................................................96
6.2.2.1 Legacy Bridge Fixed I/O Address Ranges ......................................96
6.2.2.2 Variable I/O Address Ranges.......................................................96
6.3
PCI Configuration Space .....................................................................................97
6.4
Message Bus Space............................................................................................99
7.0
Clocking ................................................................................................................. 101
7.1
Clocking Features ............................................................................................ 101
7.2
Platform/System Clock Domains ........................................................................ 102
8.0
Power Management ............................................................................................... 105
8.1
Power Management Features............................................................................. 105
8.2
Signal Descriptions .......................................................................................... 105
8.3
ACPI Supported States ..................................................................................... 106
8.3.1 S-State Definition ................................................................................. 106
8.3.1.1 S0 - Full On ............................................................................ 106
8.3.1.2 S3 - Suspend to RAM (Standby) ................................................ 106
8.3.1.3 S4 - Suspend to Disk (Hibernate) .............................................. 106
8.3.1.4 S5 - Soft Off ........................................................................... 107
8.3.2 System States...................................................................................... 107
8.3.3 Processor Idle States............................................................................. 108
8.3.4 Integrated Memory Controller States ....................................................... 108
8.3.5 PCIe* States ........................................................................................ 108
8.3.6 Interface State Combinations ................................................................. 109
8.4
Processor Core Power Management .................................................................... 109
8.4.1 Low-Power Idle States........................................................................... 109
8.4.1.1 Clock Control and Low-Power States .......................................... 109
8.4.2 Processor Core C-States Description ........................................................ 109
8.4.2.1 Core C0 State ......................................................................... 109
8.4.2.2 Core C1 State ......................................................................... 110
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8.5
9.0
8.4.2.3 Core C2 State......................................................................... 110
Memory Controller Power Management............................................................... 110
8.5.1 Disabling Unused System Memory Outputs .............................................. 110
8.5.2 DRAM Power Management and Initialization ............................................. 110
8.5.2.1 Initialization Role of CKE .......................................................... 110
8.5.2.2 Dynamic Self-Refresh .............................................................. 110
8.5.2.3 Dynamic Power Down Operation ............................................... 111
8.5.2.4 Functional Clock Gating ........................................................... 111
Power Up and Reset Sequence............................................................................... 113
9.1
Intel® Quark™ SoC X1000 System States ........................................................... 113
9.1.1 System Sleep States Control (S-States) .................................................. 113
9.2
Power Up and Down Sequences......................................................................... 113
9.2.1 Power Up, Wake and Reset Overview ...................................................... 113
9.2.2 RTC Power Well Transition: G5 to G3 State Transition ............................... 114
9.2.3 AC Power Applied: G3 to S4/S5 State Transition ....................................... 115
9.2.4 Using PWR_BTN_B: Transition from S4/S5 to S0 ...................................... 116
9.2.5 Power-Up Sequence without G2/G3: No Coin-Cell Battery .......................... 118
9.2.6 Going to Sleep: Transitions from S0 to S3 or S4/S5 .................................. 120
9.2.7 Wake Events: Transition from S3 to S0 ................................................... 120
9.2.8 System Reset Sequences....................................................................... 121
9.2.8.1 Cold Boot Sequence ............................................................... 121
9.2.8.2 Cold Reset Sequence............................................................... 121
9.2.8.3 Warm Reset Sequence (Internal) .............................................. 122
9.2.8.4 Externally Initiated Warm Reset Sequence ................................. 122
9.2.9 Handling Power Failures ........................................................................ 122
10.0 Thermal Management ............................................................................................ 123
10.1 Overview ....................................................................................................... 123
10.2 Thermal Sensor............................................................................................... 123
11.0 Processor Core ...................................................................................................... 125
12.0 Host Bridge ........................................................................................................... 127
12.1 Embedded SRAM (eSRAM)................................................................................ 127
12.1.1 Initialization ........................................................................................ 127
12.1.2 Configuration ....................................................................................... 127
12.1.2.1 4KB Page Mode ...................................................................... 127
12.1.2.2 512KB Block Page Mode........................................................... 128
12.1.3 Configuration Locking ........................................................................... 129
12.1.4 ECC Protection ..................................................................................... 130
12.1.5 Flush to DRAM ..................................................................................... 130
12.2 Isolated Memory Regions (IMR)......................................................................... 130
12.2.1 IMR Violation ....................................................................................... 131
12.2.2 IMR Locking......................................................................................... 131
12.3 Remote Management Unit DMA ......................................................................... 131
12.4 Register Map .................................................................................................. 132
12.5 PCI Configuration Registers .............................................................................. 132
12.5.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 133
12.5.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 133
12.5.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h ... 134
12.5.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 134
12.5.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 135
12.5.6 Message Bus Control Register (MCR) (SB_PACKET_REG)—Offset D0h.......... 135
12.5.7 Message Data Register (MDR) (SB_DATA_REG)—Offset D4h ...................... 136
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12.6
12.7
12.5.8 Message Control Register eXtension (MCRX) (SB_ADDR_EXTN_REG)—Offset
D8h .................................................................................................... 136
12.5.9 Manufacturer ID (PCI_MANUFACTURER)—Offset F8h ................................. 137
IO Mapped Register ......................................................................................... 138
12.6.1 ACPI Processor Block............................................................................. 138
12.6.1.1 Processor Control (P_CNT)—Offset 0h ........................................ 138
12.6.1.2 Level 2 Register (P_LVL2)—Offset 4h ......................................... 138
12.6.1.3 C6 Control Register (P_C6C)—Offset Ch ..................................... 139
12.6.2 SPI DMA Block ..................................................................................... 140
12.6.2.1 Option Register 1(P_CFG_72) —Offset 72h ................................. 140
Message Bus Register....................................................................................... 140
12.7.1 Host Bridge Arbiter (Port 0x00) .............................................................. 140
12.7.1.1 Enhanced Configuration Space (AEC_CTRL)—Offset 0h ................ 141
12.7.1.2 STATUS—Offset 21h ............................................................... 141
12.7.1.3 Requester ID Match Control (ASUBCHAN_CTRL)—Offset 50h ........ 142
12.7.1.4 Requester ID Match Sub-Channel 1 (ASUBCHAN1_MATCH)—Offset
51h ....................................................................................... 143
12.7.1.5 Requester ID Match Sub-Channel 2 (ASUBCHAN2_MATCH)—Offset
52h ....................................................................................... 143
12.7.1.6 Requester ID Match Sub-Channel 3 (ASUBCHAN3_MATCH)—Offset
53h ....................................................................................... 144
12.7.2 Host Bridge (Port 0x03) ......................................................................... 145
12.7.2.1 Host Miscellaneous Controls 2 (HMISC2)—Offset 3h .................... 146
12.7.2.2 Host System Management Mode Controls (HSMMCTL)—Offset 4h.. 147
12.7.2.3 Host Memory I/O Boundary (HMBOUND)—Offset 8h .................... 148
12.7.2.4 Extended Configuration Space (HECREG)—Offset 9h ................... 148
12.7.2.5 Miscellaneous Legacy Signal Enables (HLEGACY)—Offset Ah ......... 149
12.7.2.6 Host Bridge Write Flush Control (HWFLUSH)—Offset Ch ............... 149
12.7.2.7 MTRR Capabilities (MTRR_CAP)—Offset 40h ............................... 150
12.7.2.8 MTRR Default Type (MTRR_DEF_TYPE)—Offset 41h ..................... 151
12.7.2.9 MTRR Fixed 64KB Range 0x00000 (MTRR_FIX64K_00000)—Offset
42h ....................................................................................... 151
12.7.2.10 MTRR Fixed 64KB Range 0x40000 (MTRR_FIX64K_40000)—Offset
43h ....................................................................................... 152
12.7.2.11 MTRR Fixed 16KB Range 0x80000 (MTRR_FIX16K_80000)—Offset
44h ....................................................................................... 152
12.7.2.12 MTRR Fixed 16KB Range 0x90000 (MTRR_FIX16K_90000)—Offset
45h ....................................................................................... 153
12.7.2.13 MTRR Fixed 16KB Range 0xA0000 (MTRR_FIX16K_A0000)—Offset
46h ....................................................................................... 154
12.7.2.14 MTRR Fixed 16KB Range 0xB0000 (MTRR_FIX16K_B0000)—Offset
47h ....................................................................................... 154
12.7.2.15 MTRR Fixed 4KB Range 0xC0000 (MTRR_FIX4K_C0000)—Offset
48h ....................................................................................... 155
12.7.2.16 MTRR Fixed 4KB Range 0xC4000 (MTRR_FIX4K_C4000)—Offset
49h ....................................................................................... 155
12.7.2.17 MTRR Fixed 4KB Range 0xC8000 (MTRR_FIX4K_C8000)—Offset
4Ah ....................................................................................... 156
12.7.2.18 MTRR Fixed 4KB Range 0xCC000 (MTRR_FIX4K_CC000)—Offset
4Bh ....................................................................................... 156
12.7.2.19 MTRR Fixed 4KB Range 0xD0000 (MTRR_FIX4K_D0000)—Offset
4Ch ....................................................................................... 157
12.7.2.20 MTRR Fixed 4KB Range 0xD40000 (MTRR_FIX4K_D4000)—Offset
4Dh....................................................................................... 158
12.7.2.21 MTRR Fixed 4KB Range 0xD8000 (MTRR_FIX4K_D8000)—Offset
4Eh ....................................................................................... 158
12.7.2.22 MTRR Fixed 4KB Range 0xDC000 (MTRR_FIX4K_DC000)—Offset
4Fh ....................................................................................... 159
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12.7.2.23 MTRR Fixed 4KB Range 0xE0000 (MTRR_FIX4K_E0000)—Offset
50h....................................................................................... 159
12.7.2.24 MTRR Fixed 4KB Range 0xE4000 (MTRR_FIX4K_E4000)—Offset
51h....................................................................................... 160
12.7.2.25 MTRR Fixed 4KB Range 0xE8000 (MTRR_FIX4K_E8000)—Offset
52h....................................................................................... 160
12.7.2.26 MTRR Fixed 4KB Range 0xEC000 (MTRR_FIX4K_EC000)—Offset
53h....................................................................................... 161
12.7.2.27 MTRR Fixed 4KB Range 0xF0000 (MTRR_FIX4K_F0000)—Offset
54h....................................................................................... 161
12.7.2.28 MTRR Fixed 4KB Range 0xF4000 (MTRR_FIX4K_F4000)—Offset
55h....................................................................................... 162
12.7.2.29 MTRR Fixed 4KB Range 0xF8000 (MTRR_FIX4K_F8000)—Offset
56h....................................................................................... 163
12.7.2.30 MTRR Fixed 4KB Range 0xFC000 (MTRR_FIX4K_FC000)—Offset
57h....................................................................................... 163
12.7.2.31 System Management Range Physical Base
(MTRR_SMRR_PHYSBASE)—Offset 58h ...................................... 164
12.7.2.32 System Management Range Physical Mask
(MTRR_SMRR_PHYSMASK)—Offset 59h...................................... 164
12.7.2.33 MTRR Variable Range Physical Base 0
(MTRR_VAR_PHYSBASE0)—Offset 5Ah....................................... 165
12.7.2.34 MTRR Variable Range Physical Mask 0 (MTRR_VAR_PHYSMASK0)—
Offset 5Bh ............................................................................. 165
12.7.2.35 MTRR Variable Range Physical Base 1
(MTRR_VAR_PHYSBASE1)—Offset 5Ch....................................... 166
12.7.2.36 MTRR Variable Range Physical Mask 1 (MTRR_VAR_PHYSMASK1)—
Offset 5Dh ............................................................................. 167
12.7.2.37 MTRR Variable Range Physical Base 2
(MTRR_VAR_PHYSBASE2)—Offset 5Eh ....................................... 167
12.7.2.38 MTRR Variable Range Physical Mask 2 (MTRR_VAR_PHYSMASK2)—
Offset 5Fh.............................................................................. 168
12.7.2.39 MTRR Variable Range Physical Base 3
(MTRR_VAR_PHYSBASE3)—Offset 60h ....................................... 168
12.7.2.40 MTRR Variable Range Physical Mask 3 (MTRR_VAR_PHYSMASK3)—
Offset 61h ............................................................................. 169
12.7.2.41 MTRR Variable Range Physical Base 4
(MTRR_VAR_PHYSBASE4)—Offset 62h ....................................... 169
12.7.2.42 MTRR Variable Range Physical Mask 4 (MTRR_VAR_PHYSMASK4)—
Offset 63h ............................................................................. 170
12.7.2.43 MTRR Variable Range Physical Base 5
(MTRR_VAR_PHYSBASE5)—Offset 64h ....................................... 171
12.7.2.44 MTRR Variable Range Physical Mask 5 (MTRR_VAR_PHYSMASK5)—
Offset 65h ............................................................................. 171
12.7.2.45 MTRR Variable Range Physical Base 6
(MTRR_VAR_PHYSBASE6)—Offset 66h ....................................... 172
12.7.2.46 MTRR Variable Range Physical Mask 6 (MTRR_VAR_PHYSMASK6)—
Offset 67h ............................................................................. 172
12.7.2.47 MTRR Variable Range Physical Base 7
(MTRR_VAR_PHYSBASE7)—Offset 68h ....................................... 173
12.7.2.48 MTRR Variable Range Physical Mask 7 (MTRR_VAR_PHYSMASK7)—
Offset 69h ............................................................................. 173
12.7.3 Remote Management Unit (Port 0x04) .................................................... 174
12.7.3.1 SPI DMA Count Register (P_CFG_60)—Offset 60h........................ 174
12.7.3.2 SPI DMA Destination Register (P_CFG_61)—Offset 61h ................ 175
12.7.3.3 SPI DMA Source Register (P_CFG_62)—Offset 62h ...................... 175
12.7.3.4 Processor Register Block (P_BLK) Base Address
(P_CFG_70)—Offset 70h .......................................................... 176
12.7.3.5 Control Register (P_CFG_71)—Offset 71h................................... 176
12.7.3.6 Watchdog Control Register (P_CFG_74)—Offset 74h .................... 177
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12.7.3.7 Thermal Sensor Mode Register (P_CFG_B0)—Offset B0h............... 178
12.7.3.8 Thermal Sensor Temperature Register (P_CFG_B1)—Offset B1h .... 178
12.7.3.9 Thermal Sensor Programmable Trip Point Register
(P_CFG_B2)—Offset B2h .......................................................... 179
12.7.4 Memory Manager (Port 0x05) ................................................................. 180
12.7.4.1 Control (BCTRL)—Offset 1h ...................................................... 181
12.7.4.2 Write Flush Policy (BWFLUSH)—Offset 2h ................................... 182
12.7.4.3 Isolated Memory Region Violation Control (BIMRVCTL)—Offset 19h 183
12.7.4.4 Debug 1 (DEBUG1)—Offset 31h ................................................ 184
12.7.4.5 Isolated Memory Region 0 Low Address (IMR0L)—Offset 40h ........ 186
12.7.4.6 Isolated Memory Region 0 High Address (IMR0H)—Offset 41h ....... 186
12.7.4.7 Isolated Memory Region 0 Read Mask (IMR0RM)—Offset 42h ........ 187
12.7.4.8 Isolated Memory Region 0 Write Mask (IMR0WM)—Offset 43h ....... 189
12.7.4.9 Isolated Memory Region 1 Low Address (IMR1L)—Offset 44h ........ 190
12.7.4.10 Isolated Memory Region 1 High Address (IMR1H)—Offset 45h.... 191
12.7.4.11 Isolated Memory Region 1 Read Mask (IMR1RM)—Offset 46h..... 191
12.7.4.12 Isolated Memory Region 1 Write Mask (IMR1WM)—Offset 47h ... 193
12.7.4.13 Isolated Memory Region 2 Low Address (IMR2L)—Offset 48h ..... 195
12.7.4.14 Isolated Memory Region 2 High Address (IMR2H)—Offset 49h.... 196
12.7.4.15 Isolated Memory Region 2 Read Mask (IMR2RM)—Offset 4Ah..... 196
12.7.4.16 Isolated Memory Region 2 Write Mask (IMR2WM)—Offset 4Bh ... 198
12.7.4.17 Isolated Memory Region 3 Low Address (IMR3L)—Offset 4Ch ..... 200
12.7.4.18 Isolated Memory Region 3 High Address (IMR3H)—Offset 4Dh ... 200
12.7.4.19 Isolated Memory Region 3 Read Mask (IMR3RM)—Offset 4Eh..... 201
12.7.4.20 Isolated Memory Region 3 Write Mask (IMR3WM)—Offset 4Fh.... 203
12.7.4.21 Isolated Memory Region 4 Low Address (IMR4L)—Offset 50h ..... 204
12.7.4.22 Isolated Memory Region 4 High Address (IMR4H)—Offset 51h.... 205
12.7.4.23 Isolated Memory Region 4 Read Mask (IMR4RM)—Offset 52h..... 205
12.7.4.24 Isolated Memory Region 4 Write Mask (IMR4WM)—Offset 53h ... 207
12.7.4.25 Isolated Memory Region 5 Low Address (IMR5L)—Offset 54h ..... 209
12.7.4.26 Isolated Memory Region 5 High Address (IMR5H)—Offset 55h.... 210
12.7.4.27 Isolated Memory Region 5 Read Mask (IMR5RM)—Offset 56h..... 210
12.7.4.28 Isolated Memory Region 5 Write Mask (IMR5WM)—Offset 57h ... 212
12.7.4.29 Isolated Memory Region 6 Low Address (IMR6L)—Offset 58h ..... 214
12.7.4.30 Isolated Memory Region 6 High Address (IMR6H)—Offset 59h.... 214
12.7.4.31 Isolated Memory Region 6 Read Mask (IMR6RM)—Offset 5Ah..... 215
12.7.4.32 Isolated Memory Region 6 Write Mask (IMR6WM)—Offset 5Bh ... 217
12.7.4.33 Isolated Memory Region 7 Low Address (IMR7L)—Offset 5Ch ..... 218
12.7.4.34 Isolated Memory Region 7 High Address (IMR7H)—Offset 5Dh ... 219
12.7.4.35 Isolated Memory Region 7 Read Mask (IMR7RM)—Offset 5Eh..... 219
12.7.4.36 Isolated Memory Region 7 Write Mask (IMR7WM)—Offset 5Fh.... 221
12.7.4.37 eSRAM Control (ESRAMCTRL)—Offset 81h ............................... 223
12.7.4.38 eSRAM Block Page Control (ESRAMPGCTRL_BLOCK)—Offset 82h 224
12.7.4.39 eSRAM Correctable Error (ESRAMCERR)—Offset 83h................. 226
12.7.4.40 eSRAM Uncorrectable Error (ESRAMUERR)—Offset 84h ............. 226
12.7.4.41 eSRAM ECC Error Syndrome (ESRAMSDROME)—Offset 88h ....... 227
12.7.5 Memory Manager eSRAM (Port 0x05) ...................................................... 228
12.7.5.1 eSRAM Page Control Register[0-127]
(ESRAMPGCTRL[0-127])—Offset 0h, Count 128, Stride 4h ............ 228
12.7.6 SoC Unit (Port 0x31) ............................................................................. 229
12.7.6.1 Thermal Sensor Configuration 4 (SCU_TSCFG4_Config)—Offset
34h ....................................................................................... 229
12.7.6.2 Sticky Write Once (CFGSTICKY_W1)—Offset 50h ......................... 230
12.7.6.3 Sticky Read/Write (CFGSTICKY_RW)—Offset 51h......................... 231
12.7.6.4 Non-Sticky Read/Write Once (CFGNONSTICKY_W1)—Offset 52h .... 231
13.0 System Memory Controller ..................................................................................... 233
13.1 Signal Descriptions .......................................................................................... 233
13.2 Features ......................................................................................................... 234
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13.3
13.4
13.5
13.2.1 System Memory Technology Supported ................................................... 234
13.2.2 Rules for Populating Memory Down Ranks................................................ 235
13.2.3 DRAM Error Detection & Correction (EDC)................................................ 235
13.2.4 DRAM Data Scrambling ......................................................................... 236
13.2.5 Power Management .............................................................................. 236
Register Map .................................................................................................. 236
Message Bus Registers..................................................................................... 236
13.4.1 DRAM Rank Population (DRP)—Offset 0h ................................................. 237
13.4.2 DRAM Timing Register 0 (DTR0)—Offset 1h ............................................. 238
13.4.3 DRAM Timing Register 1 (DTR1)—Offset 2h ............................................. 240
13.4.4 DRAM Timing Register 2 (DTR2)—Offset 3h ............................................. 242
13.4.5 DRAM Timing Register 3 (DTR3)—Offset 4h ............................................. 243
13.4.6 DRAM Timing Register 4 (DTR4)—Offset 5h ............................................. 244
13.4.7 DRAM Power Management Control 0 (DPMC0)—Offset 6h........................... 245
13.4.8 DRAM Refresh Control (DRFC)—Offset 8h ................................................ 247
13.4.9 DRAM Scheduler Control (DSCH)—Offset 9h............................................. 248
13.4.10 DRAM Calibration Control (DCAL)—Offset Ah .......................................... 249
13.4.11 DRAM Reset Management Control (DRMC)—Offset Bh.............................. 250
13.4.12 Power Management Status (PMSTS)—Offset Ch ...................................... 251
13.4.13 DRAM Control Operation (DCO)—Offset Fh ............................................. 252
13.4.14 Sticky Scratchpad 0 (SSKPD0)—Offset 4Ah ............................................ 252
13.4.15 Sticky Scratchpad 1 (SSKPD1)—Offset 4Bh ............................................ 253
13.4.16 DRAM ECC Control Register (DECCCTRL)—Offset 60h .............................. 253
13.4.17 DRAM ECC Status (DECCSTAT)—Offset 61h............................................ 254
13.4.18 DRAM ECC Single Bit Error Count (DECCSBECNT)—Offset 62h .................. 254
13.4.19 DRAM Single Bit ECC Error Captured Address (DECCSBECA)—Offset 68h.... 255
13.4.20 DRAM Single Bit ECC Error Captured Syndrome (DECCSBECS)—Offset 69h. 256
13.4.21 DRAM Double Bit ECC Error Captured Address (DECCDBECA)—Offset 6Ah .. 256
13.4.22 DRAM Double Bit ECC Error Captured Syndrome (DECCDBECS)—Offset 6Bh 257
13.4.23 Memory Controller Fuse Status (DFUSESTAT)—Offset 70h ........................ 257
13.4.24 Scrambler Seed (DSCRMSEED)—Offset 80h............................................ 258
Message Bus Commands .................................................................................. 259
14.0 PCI Express* 2.0 ................................................................................................... 261
14.1 Signal Descriptions .......................................................................................... 261
14.2 Features ........................................................................................................ 261
14.2.1 Interrupts and Events ........................................................................... 262
14.2.1.1 Express Card Hot Plug Events ................................................... 262
14.2.1.2 System Error (SERR)............................................................... 263
14.2.2 Power Management .............................................................................. 263
14.3 References ..................................................................................................... 263
14.4 Register Map .................................................................................................. 263
14.5 PCI Configuration Registers .............................................................................. 264
14.5.1 Identifiers (ID)—Offset 0h ..................................................................... 266
14.5.2 Primary Status (CMD_PSTS)—Offset 4h................................................... 266
14.5.3 Class Code (RID_CC)—Offset 8h............................................................. 268
14.5.4 Header Type (CLS_PLT_HTYPE)—Offset Ch .............................................. 268
14.5.5 Secondary Latency Timer (BNUM_SLT)—Offset 18h .................................. 269
14.5.6 Secondary Status (IOBL_SSTS)—Offset 1Ch ............................................ 269
14.5.7 Memory Base and Limit (MBL)—Offset 20h .............................................. 270
14.5.8 Prefetchable Memory Base and Limit (PMBL)—Offset 24h........................... 271
14.5.9 Prefetchable Memory Base Upper 32 Bits (PMBU32)—Offset 28h ................. 271
14.5.10 Prefetchable Memory Limit Upper 32 Bits (PMLU32)—Offset 2Ch ............... 272
14.5.11 Capabilities List Pointer (CAPP)—Offset 34h............................................ 272
14.5.12 Bridge Control (INTR_BCTRL)—Offset 3Ch.............................................. 273
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Intel® Quark™ SoC X1000—Contents
14.5.13
14.5.14
14.5.15
14.5.16
14.5.17
14.5.18
14.5.19
14.5.20
14.5.21
14.5.22
14.5.23
14.5.24
14.5.25
14.5.26
14.5.27
14.5.28
14.5.29
14.5.30
14.5.31
14.5.32
14.5.33
14.5.34
14.5.35
14.5.36
14.5.37
14.5.38
14.5.39
14.5.40
14.5.41
14.5.42
14.5.43
14.5.44
14.5.45
14.5.46
14.5.47
14.5.48
14.5.49
14.5.50
14.5.51
14.5.52
14.5.53
PCI Express Capabilities (CLIST_XCAP)—Offset 40h ................................. 274
Device Capabilities (DCAP)—Offset 44h .................................................. 275
Device Status (DCTL_DSTS)—Offset 48h ................................................ 276
Link Capabilities (LCAP)—Offset 4Ch ...................................................... 277
Link Status (LCTL_LSTS)—Offset 50h..................................................... 279
Slot Capabilities (SLCAP)—Offset 54h..................................................... 280
Slot Status (SLCTL_SLSTS)—Offset 58h ................................................. 281
Root Control (RCTL)—Offset 5Ch ........................................................... 283
Root Status (RSTS)—Offset 60h ............................................................ 283
Device Capabilities 2 (DCAP2)—Offset 64h.............................................. 284
Device Status 2 (DCTL2_DSTS2)—Offset 68h.......................................... 285
Link Capability 2 (LCAP2)—Offset 6Ch.................................................... 286
Link Status 2 (LCTL2_LSTS2)—Offset 70h .............................................. 286
Slot Capabilities 2 (SLCAP2)—Offset 74h ................................................ 288
Slot Status 2 (SLCTL2_SLSTS2)—Offset 78h ........................................... 288
Message Signaled Interrupt Message Control (MID_MC)—Offset 80h .......... 289
Message Signaled Interrupt Message Address (MA)—Offset 84h................. 289
Message Signaled Interrupt Message Data (MD)—Offset 88h..................... 290
Subsystem Vendor Capability (SVCAP)—Offset 90h.................................. 290
Subsystem Vendor IDs (SVID)—Offset 94h ............................................. 291
PCI Power Management Capabilities (PMCAP_PMC)—Offset A0h................. 291
PCI Power Management Control And Status (PMCS)—Offset A4h................ 292
Channel Configuration (CCFG)—Offset D0h ............................................. 293
Miscellaneous Port Configuration 2 (MPC2)—Offset D4h ............................ 294
Miscellaneous Port Configuration (MPC)—Offset D8h ................................ 295
SMI / SCI Status (SMSCS)—Offset DCh.................................................. 296
Message Bus Control (PHYCTL_PHYCTL2_IOSFSBCTL)—Offset F4h ............. 297
Advanced Error Reporting Capability Header (AECH)—Offset 100h ............. 298
Uncorrectable Error Status (UES)—Offset 104h ....................................... 299
Uncorrectable Error Mask (UEM)—Offset 108h......................................... 300
Uncorrectable Error Severity (UEV)—Offset 10Ch..................................... 301
Correctable Error Status (CES)—Offset 110h........................................... 302
Correctable Error Mask (CEM)—Offset 114h ............................................ 303
Advanced Error Capabilities and Control (AECC)—Offset 118h ................... 304
Header Log (HL_DW1)—Offset 11Ch ...................................................... 304
Header Log (HL_DW2)—Offset 120h ...................................................... 305
Header Log (HL_DW3)—Offset 124h ...................................................... 305
Header Log (HL_DW4)—Offset 128h ...................................................... 305
Root Error Command (REC)—Offset 12Ch ............................................... 306
Root Error Status (RES)—Offset 130h .................................................... 306
Error Source Identification (ESID)—Offset 134h ...................................... 307
15.0 10/100 Mbps Ethernet ........................................................................................... 309
15.1 Signal Descriptions .......................................................................................... 309
15.2 Features:........................................................................................................ 309
15.3 References...................................................................................................... 310
15.4 Register Map ................................................................................................... 311
15.5 PCI Configuration Registers ............................................................................... 311
15.5.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 312
15.5.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 313
15.5.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 313
15.5.4 Status Register (STATUS)—Offset 6h....................................................... 314
15.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 315
15.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 315
15.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 315
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15.6
15.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 316
15.5.9 BIST (BIST)—Offset Fh ......................................................................... 316
15.5.10 Base Address Register (BAR0)—Offset 10h ............................................. 317
15.5.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 317
15.5.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 318
15.5.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 318
15.5.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 318
15.5.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 319
15.5.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 319
15.5.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 320
15.5.18 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 320
15.5.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 320
15.5.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 321
15.5.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 321
15.5.22 Power Management Capabilities (PMC)—Offset 82h ................................. 321
15.5.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 322
15.5.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 323
15.5.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 323
15.5.26 Capability ID (MSI_CAP_ID)—Offset A0h................................................ 324
15.5.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 324
15.5.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 324
15.5.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 325
15.5.30 Message Data (MESSAGE_DATA)—Offset A8h......................................... 325
15.5.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 326
15.5.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 326
Memory Mapped Registers ................................................................................ 327
15.6.1 MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h............ 331
15.6.2 MAC Frame Filter (Register 1) (GMAC_REG_1)—Offset 4h .......................... 334
15.6.3 Hash Table High Register (Register 2) (GMAC_REG_2)—Offset 8h ............... 336
15.6.4 Hash Table Low Register (Register 3) (GMAC_REG_3)—Offset Ch ............... 336
15.6.5 GMII Address Register (Register 4) (GMAC_REG_4)—Offset 10h ................. 337
15.6.6 GMII Data Register (Register 5) (GMAC_REG_5)—Offset 14h ..................... 338
15.6.7 Flow Control Register (Register 6) (GMAC_REG_6)—Offset 18h .................. 339
15.6.8 VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch ...................... 340
15.6.9 Version Register (Register 8) (GMAC_REG_8)—Offset 20h ......................... 341
15.6.10 Debug Register (Register 9) (GMAC_REG_9)—Offset 24h......................... 342
15.6.11 Interrupt Register (Register 14) (GMAC_REG_14)—Offset 38h.................. 343
15.6.12 Interrupt Mask Register (Register 15) (GMAC_REG_15)—Offset 3Ch ......... 344
15.6.13 MAC Address0 High Register (Register 16) (GMAC_REG_16)—Offset 40h ... 345
15.6.14 MAC Address0 Low Register (Register 17) (GMAC_REG_17)—Offset 44h .... 345
15.6.15 MMC Control Register (Register 64) (GMAC_REG_64)—Offset 100h ........... 346
15.6.16 MMC Receive Interrupt Register (MMC_INTR_RX)—Offset 104h ................ 347
15.6.17 MMC Transmit Interrupt Register (MMC_INTR_TX)—Offset 108h ............... 349
15.6.18 MMC Receive Interrupt Mask Register
(MMC_INTR_MASK_RX)—Offset 10Ch ................................................... 351
15.6.19 MMC Transmit Interrupt Mask Register
(MMC_INTR_MASK_TX)—Offset 110h.................................................... 353
15.6.20 MMC Transmit Good Bad Octet Counter Register
(TXOCTETCOUNT_GB)—Offset 114h........................................................ 355
15.6.21 MMC Transmit Good Bad Frame Counter Register
(TXFRAMECOUNT_GB)—Offset 118h ....................................................... 355
15.6.22 MMC Transmit Broadcast Good Frame Counter Register
(TXBROADCASTFRAMES_G)—Offset 11Ch................................................ 356
15.6.23 MMC Transmit Multicast Good Frame Counter Register
(TXMULTICASTFRAMES_G)—Offset 120h ................................................. 356
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15.6.24 MMC Transmit 64 Octet Good Bad Frame Counter Register
(TX64OCTETS_GB)—Offset 124h ............................................................ 357
15.6.25 MMC Transmit 65 to 127 Octet Good Bad Frame Counter Register
(TX65TO127OCTETS_GB)—Offset 128h ................................................... 357
15.6.26 MMC Transmit 128 to 255 Octet Good Bad Frame Counter Register
(TX128TO255OCTETS_GB)—Offset 12Ch ................................................. 358
15.6.27 MMC Transmit 256 to 511 Octet Good Bad Frame Counter Register
(TX256TO511OCTETS_GB)—Offset 130h.................................................. 358
15.6.28 MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Register
(TX512TO1023OCTETS_GB)—Offset 134h ................................................ 358
15.6.29 MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Register
(TX1024TOMAXOCTETS_GB)—Offset 138h ............................................... 359
15.6.30 MMC Transmit Unicast Good Bad Frame Counter Register
(TXUNICASTFRAMES_GB)—Offset 13Ch ................................................... 359
15.6.31 MMC Transmit Multicast Good Bad Frame Counter Register
(TXMULTICASTFRAMES_GB)—Offset 140h................................................ 360
15.6.32 MMC Transmit Broadcast Good Bad Frame Counter Register
(TXBROADCASTFRAMES_GB)—Offset 144h .............................................. 360
15.6.33 MMC Transmit Underflow Error Frame Counter Register
(TXUNDERFLOWERROR)—Offset 148h ..................................................... 361
15.6.34 MMC Transmit Single Collision Good Frame Counter Register
(TXSINGLECOL_G)—Offset 14Ch............................................................. 361
15.6.35 MMC Transmit Multiple Collision Good Frame Counter Register
(TXMULTICOL_G)—Offset 150h............................................................... 362
15.6.36 MMC Transmit Deferred Frame Counter Register (TXDEFERRED)—Offset
154h ................................................................................................... 362
15.6.37 MMC Transmit Late Collision Frame Counter Register (TXLATECOL)—Offset
158h ................................................................................................... 362
15.6.38 MMC Transmit Excessive Collision Frame Counter Register
(TXEXESSCOL)—Offset 15Ch .................................................................. 363
15.6.39 MMC Transmit Carrier Error Frame Counter Register
(TXCARRIERERROR)—Offset 160h........................................................... 363
15.6.40 MMC Transmit Good Octet Counter Register (TXOCTETCOUNT_G)—Offset
164h ................................................................................................... 364
15.6.41 MMC Transmit Good Frame Counter Register (TXFRAMECOUNT_G)—Offset
168h ................................................................................................... 364
15.6.42 MMC Transmit Excessive Deferral Frame Counter Register (TXEXCESSDEF)—
Offset 16Ch ......................................................................................... 365
15.6.43 MMC Transmit Pause Frame Counter Register (TXPAUSEFRAMES)—Offset
170h ................................................................................................... 365
15.6.44 MMC Transmit VLAN Good Frame Counter Register
(TXVLANFRAMES_G)—Offset 174h .......................................................... 366
15.6.45 MMC Transmit Oversize Good Frame Counter Register
(TXOVERSIZE_G)—Offset 178h............................................................... 366
15.6.46 MMC Receive Good Bad Frame Counter Register
(RXFRAMECOUNT_GB)—Offset 180h........................................................ 366
15.6.47 MMC Receive Good Bad Octet Counter Register
(RXOCTETCOUNT_GB)—Offset 184h........................................................ 367
15.6.48 MMC Receive Good Octet Counter Register (RXOCTETCOUNT_G)—Offset
188h ................................................................................................... 367
15.6.49 MMC Receive Broadcast Good Frame Counter Register
(RXBROADCASTFRAMES_G)—Offset 18Ch ................................................ 368
15.6.50 MMC Receive Multicast Good Frame Counter Register
(RXMULTICASTFRAMES_G)—Offset 190h ................................................. 368
15.6.51 MMC Receive CRC Error Frame Counter Register (RXCRCERROR)—Offset
194h ................................................................................................... 369
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15.6.52 MMC Receive Alignment Error Frame Counter Register
(RXALIGNMENTERROR)—Offset 198h ...................................................... 369
15.6.53 MMC Receive Runt Frame Counter Register (RXRUNTERROR)—Offset 19Ch 370
15.6.54 MMC Receive Jabber Error Frame Counter Register
(RXJABBERERROR)—Offset 1A0h ............................................................ 370
15.6.55 MMC Receive Undersize Good Frame Counter Register
(RXUNDERSIZE_G)—Offset 1A4h............................................................ 370
15.6.56 MMC Receive Oversize Good Frame Counter Register
(RXOVERSIZE_G)—Offset 1A8h.............................................................. 371
15.6.57 MMC Receive 64 Octet Good Bad Frame Counter Register
(RX64OCTETS_GB)—Offset 1ACh ........................................................... 371
15.6.58 MMC Receive 65 to 127 Octet Good Bad Frame Counter Register
(RX65TO127OCTETS_GB)—Offset 1B0h................................................... 372
15.6.59 MMC Receive 128 to 255 Octet Good Bad Frame Counter Register
(RX128TO255OCTETS_GB)—Offset 1B4h ................................................. 372
15.6.60 MMC Receive 256 to 511 Octet Good Bad Frame Counter Register
(RX256TO511OCTETS_GB)—Offset 1B8h ................................................. 373
15.6.61 MMC Receive 512 to 1023 Octet Good Bad Frame Counter Register
(RX512TO1023OCTETS_GB)—Offset 1BCh ............................................... 373
15.6.62 MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Register
(RX1024TOMAXOCTETS_GB)—Offset 1C0h .............................................. 374
15.6.63 MMC Receive Unicast Good Frame Counter Register (RXUNICASTFRAMES_G)—
Offset 1C4h ......................................................................................... 374
15.6.64 MMC Receive Length Error Frame Counter Register
(RXLENGTHERROR)—Offset 1C8h ........................................................... 374
15.6.65 MMC Receive Out Of Range Error Frame Counter Register
(RXOUTOFRANGETYPE)—Offset 1CCh...................................................... 375
15.6.66 MMC Receive Pause Frame Counter Register (RXPAUSEFRAMES)—Offset
1D0h .................................................................................................. 375
15.6.67 MMC Receive FIFO Overflow Frame Counter Register
(RXFIFOOVERFLOW)—Offset 1D4h.......................................................... 376
15.6.68 MMC Receive VLAN Good Bad Frame Counter Register (RXVLANFRAMES_GB)—
Offset 1D8h......................................................................................... 376
15.6.69 MMC Receive Watchdog Error Frame Counter Register
(RXWATCHDOGERROR)—Offset 1DCh ..................................................... 377
15.6.70 MMC Receive Error Frame Counter Register (RXRCVERROR)—Offset 1E0h .. 377
15.6.71 MMC Receive Control Frame Counter Register (RXCTRLFRAMES_G)—Offset
1E4h .................................................................................................. 378
15.6.72 MMC IPC Receive Checksum Offload Interrupt Mask Register
(MMC_IPC_INTR_MASK_RX)—Offset 200h ............................................... 378
15.6.73 MMC Receive Checksum Offload Interrupt Register
(MMC_IPC_INTR_RX)—Offset 208h......................................................... 380
15.6.74 MMC Receive IPV4 Good Frame Counter Register
(RXIPV4_GD_FRMS)—Offset 210h .......................................................... 382
15.6.75 MMC Receive IPV4 Header Error Frame Counter Register
(RXIPV4_HDRERR_FRMS)—Offset 214h ................................................... 383
15.6.76 MMC Receive IPV4 No Payload Frame Counter Register
(RXIPV4_NOPAY_FRMS)—Offset 218h ..................................................... 383
15.6.77 MMC Receive IPV4 Fragmented Frame Counter Register
(RXIPV4_FRAG_FRMS)—Offset 21Ch ....................................................... 384
15.6.78 MMC Receive IPV4 UDP Checksum Disabled Frame Counter Register
(RXIPV4_UDSBL_FRMS)—Offset 220h ..................................................... 384
15.6.79 MMC Receive IPV6 Good Frame Counter Register
(RXIPV6_GD_FRMS)—Offset 224h .......................................................... 384
15.6.80 MMC Receive IPV6 Header Error Frame Counter Register
(RXIPV6_HDRERR_FRMS)—Offset 228h ................................................... 385
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15.6.81 MMC Receive IPV6 No Payload Frame Counter Register
(RXIPV6_NOPAY_FRMS)—Offset 22Ch ..................................................... 385
15.6.82 MMC Receive UDP Good Frame Counter Register (RXUDP_GD_FRMS)—Offset
230h ................................................................................................... 386
15.6.83 MMC Receive UDP Error Frame Counter Register
(RXUDP_ERR_FRMS)—Offset 234h .......................................................... 386
15.6.84 MMC Receive TCP Good Frame Counter Register (RXTCP_GD_FRMS)—Offset
238h ................................................................................................... 387
15.6.85 MMC Receive TCP Error Frame Counter Register (RXTCP_ERR_FRMS)—Offset
23Ch................................................................................................... 387
15.6.86 MMC Receive ICMP Good Frame Counter Register
(RXICMP_GD_FRMS)—Offset 240h .......................................................... 388
15.6.87 MMC Receive ICMP Error Frame Counter Register
(RXICMP_ERR_FRMS)—Offset 244h......................................................... 388
15.6.88 MMC Receive IPV4 Good Octet Counter Register
(RXIPV4_GD_OCTETS)—Offset 250h ....................................................... 388
15.6.89 MMC Receive IPV4 Header Error Octet Counter Register
(RXIPV4_HDRERR_OCTETS)—Offset 254h ................................................ 389
15.6.90 MMC Receive IPV4 No Payload Octet Counter Register
(RXIPV4_NOPAY_OCTETS)—Offset 258h .................................................. 389
15.6.91 MMC Receive IPV4 Fragmented Octet Counter Register
(RXIPV4_FRAG_OCTETS)—Offset 25Ch .................................................... 390
15.6.92 MMC Receive IPV4 UDP Checksum Disabled Octet Counter Register
(RXIPV4_UDSBL_OCTETS)—Offset 260h .................................................. 390
15.6.93 MMC Receive IPV6 Good Octet Counter Register
(RXIPV6_GD_OCTETS)—Offset 264h ....................................................... 391
15.6.94 MMC Receive IPV6 Good Octet Counter Register (RXIPV6_HDRERR_OCTETS)—
Offset 268h.......................................................................................... 391
15.6.95 MMC Receive IPV6 Header Error Octet Counter Register
(RXIPV6_NOPAY_OCTETS)—Offset 26Ch .................................................. 392
15.6.96 MMC Receive IPV6 No Payload Octet Counter Register (RXUDP_GD_OCTETS)—
Offset 270h.......................................................................................... 392
15.6.97 MMC Receive UDP Good Octet Counter Register
(RXUDP_ERR_OCTETS)—Offset 274h....................................................... 392
15.6.98 MMC Receive TCP Good Octet Counter Register
(RXTCP_GD_OCTETS)—Offset 278h ........................................................ 393
15.6.99 MMC Receive TCP Error Octet Counter Register
(RXTCP_ERR_OCTETS)—Offset 27Ch ....................................................... 393
15.6.100 MMC Receive ICMP Good Octet Counter Register
(RXICMP_GD_OCTETS)—Offset 280h....................................................... 394
15.6.101 MMC Receive ICMP Error Octet Counter Register
(RXICMP_ERR_OCTETS)—Offset 284h ..................................................... 394
15.6.102 VLAN Tag Inclusion or Replacement Register (Register 353)
(GMAC_REG_353)—Offset 584h.............................................................. 395
15.6.103 VLAN Hash Table Register (Register 354) (GMAC_REG_354)—Offset 588h 396
15.6.104 Timestamp Control Register (Register 448)
(GMAC_REG_448)—Offset 700h ......................................................... 396
15.6.105 Sub-Second Increment Register (Register 449) (GMAC_REG_449)—Offset
704h ................................................................................................... 398
15.6.106 System Time - Seconds Register (Register 450) (GMAC_REG_450)—Offset
708h ................................................................................................... 398
15.6.107 System Time - Nanoseconds Register (Register 451)
(GMAC_REG_451)—Offset 70Ch ............................................................. 399
15.6.108 System Time - Seconds Update Register (Register 452) (GMAC_REG_452)—
Offset 710h.......................................................................................... 399
15.6.109 System Time - Nanoseconds Update Register (Register 453)
(GMAC_REG_453)—Offset 714h.............................................................. 400
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15.7
15.6.110 Timestamp Addend Register (Register 454)
(GMAC_REG_454)—Offset 718h ......................................................... 400
15.6.111 Target Time Seconds Register (Register 455) (GMAC_REG_455)—Offset
71Ch .................................................................................................. 401
15.6.112 Target Time Nanoseconds Register (Register 456)
(GMAC_REG_456)—Offset 720h ............................................................. 401
15.6.113 System Time - Higher Word Seconds Register (Register 457)
(GMAC_REG_457)—Offset 724h ............................................................. 402
15.6.114 Timestamp Status Register (Register 458)
(GMAC_REG_458)—Offset 728h.......................................................... 403
15.6.115 Bus Mode Register (Register 0) (DMA_REG_0)—Offset 1000h ................. 404
15.6.116 Transmit Poll Demand Register (Register 1) (DMA_REG_1)—Offset 1004h 406
15.6.117 Receive Poll Demand Register (Register 2) (DMA_REG_2)—Offset 1008h.. 406
15.6.118 Receive Descriptor List Address Register (Register 3) (DMA_REG_3)—Offset
100Ch ................................................................................................ 407
15.6.119 Transmit Descriptor List Address Register (Register 4)
(DMA_REG_4)—Offset 1010h ................................................................. 407
15.6.120 Status Register (Register 5) (DMA_REG_5)—Offset 1014h...................... 408
15.6.121 Operation Mode Register (Register 6) (DMA_REG_6)—Offset 1018h......... 411
15.6.122 Interrupt Enable Register (Register 7) (DMA_REG_7)—Offset 101Ch........ 414
15.6.123 Missed Frame and Buffer Overflow Counter Register (Register 8)
(DMA_REG_8)—Offset 1020h ................................................................. 415
15.6.124 Receive Interrupt Watchdog Timer Register (Register 9)
(DMA_REG_9)—Offset 1024h ................................................................. 416
15.6.125 AHB Status Register (Register 11) (DMA_REG_11)—Offset 102Ch ........... 416
15.6.126 Current Host Transmit Descriptor Register (Register 18)
(DMA_REG_18)—Offset 1048h ............................................................... 417
15.6.127 Current Host Receive Descriptor Register (Register 19)
(DMA_REG_19)—Offset 104Ch ............................................................... 417
15.6.128 Current Host Transmit Buffer Address Register (Register 20)
(DMA_REG_20)—Offset 1050h ............................................................... 418
15.6.129 Current Host Receive Buffer Address Register (Register 21) (DMA_REG_21)—
Offset 1054h ....................................................................................... 418
15.6.130 HW Feature Register (Register 22) (DMA_REG_22)—Offset 1058h ........... 419
MAC Descriptor Details..................................................................................... 421
15.7.1 Descriptor Overview ............................................................................. 421
15.7.2 Descriptor Endianness .......................................................................... 421
15.7.3 Transmit Descriptor ............................................................................. 421
15.7.4 Receive Descriptor ............................................................................... 427
16.0 USB 2.0 ................................................................................................................. 435
16.1 Signal Descriptions .......................................................................................... 435
16.2 Features ........................................................................................................ 435
16.2.1 USB2.0 Host Controller Features ............................................................ 435
16.2.2 USB2.0 Device Features ........................................................................ 436
16.3 References ..................................................................................................... 436
16.4 Register Map .................................................................................................. 437
16.5 PCI Configuration Registers .............................................................................. 437
16.5.1 USB Device ......................................................................................... 437
16.5.1.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 438
16.5.1.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 439
16.5.1.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 439
16.5.1.4 Status Register (STATUS)—Offset 6h......................................... 440
16.5.1.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 440
16.5.1.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 441
16.5.1.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 441
16.5.1.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 442
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16.5.1.9 BIST (BIST)—Offset Fh ............................................................ 442
16.5.1.10 Base Address Register (BAR0)—Offset 10h ............................... 443
16.5.1.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 443
16.5.1.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch........ 444
16.5.1.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 444
16.5.1.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 444
16.5.1.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ........................ 445
16.5.1.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch ....................... 445
16.5.1.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh .......................... 446
16.5.1.18 MIN_GNT (MIN_GNT)—Offset 3Eh............................................ 446
16.5.1.19 MAX_LAT (MAX_LAT)—Offset 3Fh ............................................ 446
16.5.1.20 Capability ID (PM_CAP_ID)—Offset 80h .................................... 447
16.5.1.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............. 447
16.5.1.22 Power Management Capabilities (PMC)—Offset 82h .................... 447
16.5.1.23 Power Management Control/Status Register (PMCSR)—Offset 84h 448
16.5.1.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 449
16.5.1.25 Power Management Data Register (DATA_REGISTER)—Offset 87h 449
16.5.1.26 Capability ID (MSI_CAP_ID)—Offset A0h................................... 450
16.5.1.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........... 450
16.5.1.28 Message Control (MESSAGE_CTRL)—Offset A2h ......................... 450
16.5.1.29 Message Address (MESSAGE_ADDR)—Offset A4h ....................... 451
16.5.1.30 Message Data (MESSAGE_DATA)—Offset A8h............................ 451
16.5.1.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ....................... 452
16.5.1.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h .................... 452
16.5.2 USB EHCI ............................................................................................ 453
16.5.2.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 454
16.5.2.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 454
16.5.2.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 454
16.5.2.4 Status Register (STATUS)—Offset 6h ......................................... 455
16.5.2.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 456
16.5.2.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 456
16.5.2.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 457
16.5.2.8 Header Type (HEADER_TYPE)—Offset Eh .................................... 457
16.5.2.9 BIST (BIST)—Offset Fh ............................................................ 457
16.5.2.10 Base Address Register (BAR0)—Offset 10h ............................... 458
16.5.2.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 459
16.5.2.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ....... 459
16.5.2.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 459
16.5.2.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 460
16.5.2.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ....................... 460
16.5.2.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch....................... 460
16.5.2.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh.......................... 461
16.5.2.18 MIN_GNT (MIN_GNT)—Offset 3Eh ........................................... 461
16.5.2.19 MAX_LAT (MAX_LAT)—Offset 3Fh............................................ 462
16.5.2.20 Serial Bus Release Number Register (SBRN)—Offset 60h ............ 462
16.5.2.21 Frame Length Adjustment Register (FLADJ)—Offset 61h............. 462
16.5.2.22 Capability ID (PM_CAP_ID)—Offset 80h ................................... 463
16.5.2.23 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............ 463
16.5.2.24 Power Management Capabilities (PMC)—Offset 82h.................... 463
16.5.2.25 Power Management Control/Status Register
(PMCSR)—Offset 84h............................................................. 464
16.5.2.26 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h ....................................................................................... 465
16.5.2.27 Power Management Data Register
(DATA_REGISTER)—Offset 87h ............................................... 465
16.5.2.28 Capability ID (MSI_CAP_ID)—Offset A0h .................................. 465
16.5.2.29 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h........... 466
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Contents—Intel® Quark™ SoC X1000
16.6
16.5.2.30 Message Control (MESSAGE_CTRL)—Offset A2h........................ 466
16.5.2.31 Message Address (MESSAGE_ADDR)—Offset A4h...................... 467
16.5.2.32 Message Data (MESSAGE_DATA)—Offset A8h........................... 467
16.5.2.33 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh ...................... 468
16.5.2.34 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................... 468
16.5.2.35 USB Legacy Support Extended Capability (USBLEGSUP)—Offset
C0h ...................................................................................... 468
16.5.2.36 USB Legacy Support Control/Status
(USBLEGCTLSTS)—Offset C4h ................................................ 469
16.5.3 USB OHCI ........................................................................................... 471
16.5.3.1 Vendor ID (VENDOR_ID)—Offset 0h .......................................... 472
16.5.3.2 Device ID (DEVICE_ID)—Offset 2h ............................................ 472
16.5.3.3 Command Register (COMMAND_REGISTER)—Offset 4h ................ 473
16.5.3.4 Status Register (STATUS)—Offset 6h......................................... 473
16.5.3.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .... 474
16.5.3.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ......................... 475
16.5.3.7 Latency Timer (LATENCY_TIMER)—Offset Dh .............................. 475
16.5.3.8 Header Type (HEADER_TYPE)—Offset Eh ................................... 475
16.5.3.9 BIST (BIST)—Offset Fh ............................................................ 476
16.5.3.10 Base Address Register (BAR0)—Offset 10h ............................... 476
16.5.3.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h ....... 477
16.5.3.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch........ 477
16.5.3.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ................................ 478
16.5.3.14 Expansion ROM Base Address
(EXP_ROM_BASE_ADR)—Offset 30h ........................................ 478
16.5.3.15 Capabilities Pointer (CAP_POINTER)—Offset 34h........................ 479
16.5.3.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch ....................... 479
16.5.3.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh .......................... 479
16.5.3.18 MIN_GNT (MIN_GNT)—Offset 3Eh ........................................... 480
16.5.3.19 MAX_LAT (MAX_LAT)—Offset 3Fh ............................................ 480
16.5.3.20 Capability ID (PM_CAP_ID)—Offset 80h.................................... 480
16.5.3.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h ............ 481
16.5.3.22 Power Management Capabilities (PMC)—Offset 82h .................... 481
16.5.3.23 Power Management Control/Status Register (PMCSR)—Offset 84h 482
16.5.3.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h....................................................................................... 483
16.5.3.25 Power Management Data Register (DATA_REGISTER)—Offset 87h 483
16.5.3.26 Capability ID (MSI_CAP_ID)—Offset A0h .................................. 483
16.5.3.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........... 484
16.5.3.28 Message Control (MESSAGE_CTRL)—Offset A2h ........................ 484
16.5.3.29 Message Address (MESSAGE_ADDR)—Offset A4h ...................... 484
16.5.3.30 Message Data (MESSAGE_DATA)—Offset A8h ........................... 485
16.5.3.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh....................... 485
16.5.3.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................... 486
Memory Mapped Registers ................................................................................ 486
16.6.1 USB Device ......................................................................................... 486
16.6.1.1 IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)—Offset 0h .. 489
16.6.1.2 IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)—Offset 4h .... 490
16.6.1.3 IN Endpoint 0 Buffer Size Register
(ep0_in_bufsize_udc_reg)—Offset 8h ........................................ 492
16.6.1.4 IN Endpoint 0 Maximum Packet Size Register
(ep0_in_mpkt_sz_reg)—Offset Ch............................................. 493
16.6.1.5 IN Endpoint 0 Data Descriptor Pointer Register
(ep0_in_desptr_udc_reg)—Offset 14h ....................................... 493
16.6.1.6 IN Endpoint 0 Write Confirmation register (for Slave-Only mode)
(ep0_wr_cfrm_udc_reg)—Offset 1Ch ......................................... 494
16.6.1.7 IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)—Offset 20h. 494
16.6.1.8 IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)—Offset 24h .. 495
16.6.1.9 IN Endpoint 1 Buffer Size Register
(ep1_in_bufsize_udc_reg)—Offset 28h....................................... 497
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Intel® Quark™ SoC X1000—Contents
16.6.1.10 IN Endpoint 1 Maximum Packet Size Register
(ep1_in_mpkt_sz_reg)—Offset 2Ch ........................................... 498
16.6.1.11 IN Endpoint 1 Data Descriptor Pointer Register
(ep1_in_desptr_udc_reg)—Offset 34h ........................................ 498
16.6.1.12 IN Endpoint 1 Write Confirmation register (for Slave-Only mode)
(ep1_wr_cfrm_udc_reg)—Offset 3Ch ......................................... 499
16.6.1.13 IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)—Offset 40h499
16.6.1.14 IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)—Offset 44h . 500
16.6.1.15 IN Endpoint 2 Buffer Size Register
(ep2_in_bufsize_udc_reg)—Offset 48h ....................................... 502
16.6.1.16 IN Endpoint 2 Maximum Packet Size Register
(ep2_in_mpkt_sz_reg)—Offset 4Ch ........................................... 503
16.6.1.17 IN Endpoint 2 Data Descriptor Pointer Register
(ep2_in_desptr_udc_reg)—Offset 54h ........................................ 503
16.6.1.18 IN Endpoint 2 Write Confirmation register (for Slave-Only mode)
(ep2_wr_cfrm_udc_reg)—Offset 5Ch ......................................... 504
16.6.1.19 IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)—Offset 60h504
16.6.1.20 IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)—Offset 64h . 505
16.6.1.21 IN Endpoint 3 Buffer Size Register
(ep3_in_bufsize_udc_reg)—Offset 68h ....................................... 507
16.6.1.22 IN Endpoint 3 Maximum Packet Size Register
(ep3_in_mpkt_sz_reg)—Offset 6Ch ........................................... 508
16.6.1.23 IN Endpoint 3 Data Descriptor Pointer Register
(ep3_in_desptr_udc_reg)—Offset 74h ........................................ 508
16.6.1.24 IN Endpoint 3 Write Confirmation register (for Slave-Only mode)
(ep3_wr_cfrm_udc_reg)—Offset 7Ch ......................................... 509
16.6.1.25 OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)—Offset
200h ..................................................................................... 509
16.6.1.26 OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)—Offset
204h ..................................................................................... 510
16.6.1.27 OUT Endpoint 0 Receive Packet Frame Number Register
(ep0_out_rpf_udc_reg)—Offset 208h ......................................... 512
16.6.1.28 OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)—
Offset 20Ch ............................................................................ 513
16.6.1.29 OUT Endpoint 0 SETUP Buffer Pointer Register
(ep0_subptr_udc_reg)—Offset 210h .......................................... 513
16.6.1.30 OUT Endpoint 0 Data Descriptor Pointer Register
(ep0_out_desptr_udc_reg)—Offset 214h .................................... 514
16.6.1.31 OUT Endpoint 0 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep0_rd_cfrm_udc_reg)—Offset 21Ch . 514
16.6.1.32 OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)—Offset
220h ..................................................................................... 515
16.6.1.33 OUT Endpoint 1 Status Register (ep1_out_sts_udc_reg)—Offset
224h ..................................................................................... 516
16.6.1.34 OUT Endpoint 1 Receive Packet Frame Number Register
(ep1_out_rpf_udc_reg)—Offset 228h ......................................... 518
16.6.1.35 OUT Endpoint 1 Buffer Size Register (ep1_out_bufsize_udc_reg)—
Offset 22Ch ............................................................................ 519
16.6.1.36 OUT Endpoint 1 SETUP Buffer Pointer Register
(ep1_subptr_udc_reg)—Offset 230h .......................................... 519
16.6.1.37 OUT Endpoint 1 Data Descriptor Pointer Register
(ep1_out_desptr_udc_reg)—Offset 234h .................................... 520
16.6.1.38 OUT Endpoint 1 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep1_rd_cfrm_udc_reg)—Offset 23Ch . 520
16.6.1.39 OUT Endpoint 2 Control Register (ep2_out_ctrl_udc_reg)—Offset
240h ..................................................................................... 521
16.6.1.40 OUT Endpoint 2 Status Register (ep2_out_sts_udc_reg)—Offset
244h ..................................................................................... 522
16.6.1.41 OUT Endpoint 2 Receive Packet Frame Number Register
(ep2_out_rpf_udc_reg)—Offset 248h ......................................... 524
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Contents—Intel® Quark™ SoC X1000
16.6.1.42 OUT Endpoint 2 Buffer Size Register (ep2_out_bufsize_udc_reg)—
Offset 24Ch ........................................................................... 525
16.6.1.43 OUT Endpoint 2 SETUP Buffer Pointer Register
(ep2_subptr_udc_reg)—Offset 250h .......................................... 525
16.6.1.44 OUT Endpoint 2 Data Descriptor Pointer Register
(ep2_out_desptr_udc_reg)—Offset 254h.................................... 526
16.6.1.45 OUT Endpoint 2 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep2_rd_cfrm_udc_reg)—Offset 25Ch. 526
16.6.1.46 OUT Endpoint 3 Control Register (ep3_out_ctrl_udc_reg)—Offset
260h ..................................................................................... 527
16.6.1.47 OUT Endpoint 3 Status Register (ep3_out_sts_udc_reg)—Offset
264h ..................................................................................... 528
16.6.1.48 OUT Endpoint 3 Receive Packet Frame Number Register
(ep3_out_rpf_udc_reg)—Offset 268h......................................... 530
16.6.1.49 OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)—
Offset 26Ch ........................................................................... 531
16.6.1.50 OUT Endpoint 3 SETUP Buffer Pointer Register
(ep3_subptr_udc_reg)—Offset 270h .......................................... 531
16.6.1.51 OUT Endpoint 3 Data Descriptor Pointer Register
(ep3_out_desptr_udc_reg)—Offset 274h.................................... 532
16.6.1.52 OUT Endpoint 3 Read Confirmation Register for zero-length OUT
data (for Slave-Only mode) (ep3_rd_cfrm_udc_reg)—Offset 27Ch. 532
16.6.1.53 Device Configuration Register (d_cfg_udc_reg)—Offset 400h ...... 533
16.6.1.54 Device Control Register (d_ctrl_udc_reg)—Offset 404h .............. 534
16.6.1.55 Device Status Register (d_sts_udc_reg)—Offset 408h................ 536
16.6.1.56 Device Interrupt Register (d_intr_udc_reg)—Offset 40Ch ........... 537
16.6.1.57 Device Interrupt Mask Register (d_intr_msk_udc_reg)—Offset
410h ..................................................................................... 538
16.6.1.58 Endpoints Interrupt Register (ep_intr_udc_reg)—Offset 414h ..... 539
16.6.1.59 Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)—Offset
418h ..................................................................................... 539
16.6.1.60 Test Mode Register (test_mode_udc_reg)—Offset 41Ch ............. 540
16.6.1.61 Product Release Number Register
(revision_udc_reg)—Offset 420h............................................. 541
16.6.1.62 SETUP command address pointer register
(udc_desc_addr_udc_reg)—Offset 500h..................................... 541
16.6.1.63 Physical Endpoint 0 Register
(udc_ep_ne_udc_reg_0)—Offset 504h ..................................... 542
16.6.1.64 Physical Endpoint 1 Register
(udc_ep_ne_udc_reg_1)—Offset 508h ..................................... 542
16.6.1.65 Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)—Offset
50Ch..................................................................................... 543
16.6.1.66 Physical Endpoint 3 Register
(udc_ep_ne_udc_reg_3)—Offset 510h ..................................... 544
16.6.1.67 Physical Endpoint 4 Register
(udc_ep_ne_udc_reg_4)—Offset 514h ..................................... 545
16.6.1.68 Physical Endpoint 5 Register
(udc_ep_ne_udc_reg_5)—Offset 518h ..................................... 546
16.6.1.69 Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)—Offset
51Ch..................................................................................... 546
16.6.1.70 RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])—Offset
800h, Count 512, Stride 4h ...................................................... 547
16.6.1.71 TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])—Offset
1000h, Count 256, Stride 4h .................................................... 548
16.6.1.72 TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])—Offset
1400h, Count 256, Stride 4h .................................................... 548
16.6.1.73 TxFIFO 2 Array[0-255] (udc_tx_fifo_reg_2_array[0-255])—Offset
1800h, Count 256, Stride 4h .................................................... 548
16.6.1.74 TxFIFO 3 Array[0-255] (udc_tx_fifo_reg_3_array[0-255])—Offset
1C00h, Count 256, Stride 4h .................................................... 549
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Intel® Quark™ SoC X1000—Contents
16.6.2 USB EHCI ............................................................................................ 549
16.6.2.1 Host Controller Interface Version Number and Capability Registers
Length (HCCAPBASE)—Offset 0h ............................................... 550
16.6.2.2 Host Controller Structural Parameters (HCSPARAMS)—Offset 4h .... 550
16.6.2.3 Host Controller Capability Parameters (HCCPARAMS)—Offset 8h .... 552
16.6.2.4 USB Command (USBCMD)—Offset 10h....................................... 553
16.6.2.5 USB Status (USBSTS)—Offset 14h ............................................. 555
16.6.2.6 USB Interrupt Enable (USBINTR)—Offset 18h.............................. 557
16.6.2.7 USB Frame Index (FRINDEX)—Offset 1Ch................................... 558
16.6.2.8 4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)—Offset
20h ....................................................................................... 559
16.6.2.9 Periodic Frame List Base Address (PERIODICLISTBASE)—Offset
24h ....................................................................................... 559
16.6.2.10 Asynchronous List Address (ASYNCLISTADDR)—Offset 28h ......... 560
16.6.2.11 Configure Flag (CONFIGFLAG)—Offset 50h................................ 560
16.6.2.12 Port Status/Control[0-1] (PORTSC[0-1])—Offset 54h, Count 2,
Stride 4h................................................................................ 561
16.6.2.13 Programmable Microframe Base Value (INSNREG00)—Offset 90h. 564
16.6.2.14 Programmable Packet Buffer OUT/IN Thresholds
(INSNREG01)—Offset 94h ........................................................ 565
16.6.2.15 Programmable Packet Buffer Depth (INSNREG02)—Offset 98h..... 565
16.6.2.16 Programmable Controller Settings (INSNREG03)—Offset 9Ch ...... 566
16.6.2.17 Programmable Controller Settings (INSNREG04)—Offset A0h ...... 567
16.6.2.18 UTMI Configuration (INSNREG05)—Offset A4h........................... 568
16.6.3 USB OHCI............................................................................................ 569
16.6.3.1 OHCI Revision (HCREVISION)—Offset 0h.................................... 570
16.6.3.2 Host Controller Control (HCCONTROL)—Offset 4h ........................ 570
16.6.3.3 Host Controller Command Status (HCCMDSTATUS)—Offset 8h ...... 571
16.6.3.4 Host Controller Interrupt Status (HCINTRSTATUS)—Offset Ch ....... 573
16.6.3.5 Host Controller Interrupt Enable (HCINTRENABLE)—Offset 10h...... 574
16.6.3.6 Host Controller Interrupt Disable (HCINTRDISABLE)—Offset 14h ... 575
16.6.3.7 Host Controller Communication Area (HCHCCA)—Offset 18h ......... 576
16.6.3.8 Host Controller Current Isochronous or Interrupt Endpoint
(HCPRDCURED)—Offset 1Ch ..................................................... 577
16.6.3.9 Host Controller Current First Control Endpoint (HCCTRLHEADED)—
Offset 20h .............................................................................. 577
16.6.3.10 Host Controller Current Control Endpoint (HCCTRLCURED)—Offset
24h ....................................................................................... 578
16.6.3.11 Host Controller First Bulk Endpoint (HCBULKHEADED)—Offset 28h578
16.6.3.12 Host Controller Current Bulk Endpoint (HCBULKCURED)—Offset
2Ch ....................................................................................... 579
16.6.3.13 Host Controller Last Completed Descriptor (HCDONEHEAD)—Offset
30h ....................................................................................... 580
16.6.3.14 Host Controller Frame Interval (HCFMINTERVAL)—Offset 34h ...... 580
16.6.3.15 Host Controller Remaining Frame (HCFMREMAINING)—Offset 38h 581
16.6.3.16 Host Controller Frame Number (HCFMNUMBER)—Offset 3Ch........ 582
16.6.3.17 Host Controller Periodic List Start (HCPERIODICSTART)—Offset
40h ....................................................................................... 583
16.6.3.18 Host Controller LS Threshold (HCLSTHRESHOLD)—Offset 44h ...... 583
16.6.3.19 Host Controller Root Hub Descriptor A (HCRHDESPA)—Offset 48h 584
16.6.3.20 Host Controller Root Hub Descriptor B (HCRHDESPB)—Offset 4Ch 585
16.6.3.21 Host Controller Root Hub Status (HCRHSTATUS)—Offset 50h....... 586
16.6.3.22 Host Controller Root Hub Port Status (HCRHPORTSTS)—Offset 54h ...
587
17.0 SDIO/SD/eMMC ..................................................................................................... 591
17.1 Signal Descriptions .......................................................................................... 591
17.2 Features ......................................................................................................... 592
17.2.1 SDIO/SD/eMMC Features ....................................................................... 592
17.2.2 SD 3.0/ SDIO 3.0 / eMMC 4.41 Interfaces ................................................ 592
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17.3
17.4
17.5
17.6
17.2.2.1 SD 3.0 Bus Topology ............................................................... 592
17.2.2.2 SDIO 3.0 Interface.................................................................. 593
17.2.2.3 eMMC Interface ...................................................................... 594
17.2.3 SDIO/SD/eMMC Host Controller.............................................................. 594
17.2.3.1 SD DMA................................................................................. 595
References ..................................................................................................... 595
Register Map .................................................................................................. 595
PCI Configuration Registers .............................................................................. 596
17.5.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 597
17.5.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 598
17.5.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 598
17.5.4 Status Register (STATUS)—Offset 6h ...................................................... 599
17.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 599
17.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 600
17.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 600
17.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 601
17.5.9 BIST (BIST)—Offset Fh ......................................................................... 601
17.5.10 Base Address Register (BAR0)—Offset 10h ............................................. 602
17.5.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 602
17.5.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 603
17.5.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 603
17.5.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 603
17.5.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 604
17.5.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 604
17.5.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 605
17.5.18 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 605
17.5.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 605
17.5.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 606
17.5.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 606
17.5.22 Power Management Capabilities (PMC)—Offset 82h ................................. 606
17.5.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 607
17.5.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 608
17.5.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 608
17.5.26 Capability ID (MSI_CAP_ID)—Offset A0h................................................ 609
17.5.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 609
17.5.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 609
17.5.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 610
17.5.30 Message Data (MESSAGE_DATA)—Offset A8h......................................... 610
17.5.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 611
17.5.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 611
Memory Mapped Registers ................................................................................ 612
17.6.1 SDMA System Address Register (SYS_ADR)—Offset 0h.............................. 613
17.6.2 Block Size Register (BLK_SIZE)—Offset 4h .............................................. 614
17.6.3 Block Count Register (BLK_COUNT)—Offset 6h......................................... 615
17.6.4 Argument Register (ARGUMENT)—Offset 8h............................................. 616
17.6.5 Transfer Mode Register (TX_MODE)—Offset Ch......................................... 616
17.6.6 Command Register (CMD)—Offset Eh...................................................... 618
17.6.7 Response Register 0 (RESPONSE0)—Offset 10h........................................ 619
17.6.8 Response Register 2 (RESPONSE2)—Offset 14h........................................ 620
17.6.9 Response Register 4 (RESPONSE4)—Offset 18h........................................ 620
17.6.10 Response Register 6 (RESPONSE6)—Offset 1Ch ...................................... 621
17.6.11 Buffer Data Port Register (BUF_DATA_PORT)—Offset 20h......................... 621
17.6.12 Present State Register (PRE_STATE)—Offset 24h .................................... 622
17.6.13 Host Control Register (HOST_CTL)—Offset 28h ....................................... 627
17.6.14 Power Control Register (PWR_CTL)—Offset 29h ...................................... 628
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17.6.15
17.6.16
17.6.17
17.6.18
17.6.19
17.6.20
17.6.21
17.6.22
17.6.23
17.6.24
17.6.25
17.6.26
17.6.27
17.6.28
17.6.29
17.6.30
Block Gap Control Register (BLK_GAP_CTL)—Offset 2Ah ........................... 628
Clock Control Register (CLK_CTL)—Offset 2Ch......................................... 630
Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh.............................. 632
Software Reset Register (SW_RST)—Offset 2Fh ....................................... 633
Normal Interrupt Status Register (NML_INT_STATUS)—Offset 30h ............. 634
Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h ................ 636
Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—Offset 34h ......... 638
Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—Offset 36h .... 639
Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—Offset 38h ... 640
Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—Offset 3Ah....... 642
Auto CMD12 Error Status Register (CMD12_ERR_STAT)—Offset 3Ch .......... 643
Host Control 2 Register (HOST_CTRL_2)—Offset 3Eh ............................... 644
Capabilities Register (CAPABILITIES)—Offset 40h .................................... 645
Capabilities Register 2 (CAPABILITIES_2)—Offset 44h .............................. 647
Maximum Current Capabilities Register (MAX_CUR_CAP)—Offset 48h ......... 648
Force Event Register for Auto CMD12 Error Status
(FORCE_EVENT_CMD12_ERR_STAT)—Offset 50h ...................................... 649
17.6.31 Force Event Register for Error Interrupt Status
(FORCE_EVENT_ERR_INT_STAT)—Offset 52h ........................................... 650
17.6.32 ADMA Error Status Register (ADMA_ERR_STAT)—Offset 54h ..................... 651
17.6.33 ADMA System Address Register (ADMA_SYS_ADDR)—Offset 58h ............... 652
17.6.34 initialization Preset Values Register (3.3v or 1.8v)
(PRESET_VALUE_0)—Offset 60h ............................................................. 653
17.6.35 Default Speed Preset Values Register (PRESET_VALUE_1)—Offset 62h ....... 653
17.6.36 High Speed Preset Values Register (PRESET_VALUE_2)—Offset 64h ........... 654
17.6.37 SDR12 Preset Values Register (PRESET_VALUE_3)—Offset 66h.................. 654
17.6.38 SDR25 Preset Values Register (PRESET_VALUE_4)—Offset 68h.................. 655
17.6.39 SDR50 Preset Values Register (PRESET_VALUE_5)—Offset 6Ah ................. 656
17.6.40 SDR104 Preset Values Register (PRESET_VALUE_6)—Offset 6Ch................ 656
17.6.41 DDR50 Preset Values Register (PRESET_VALUE_7)—Offset 6Eh ................. 657
17.6.42 Boot Time-out control register (BOOT_TIMEOUT_CTRL)—Offset 70h........... 658
17.6.43 Debug Selection Register (DEBUG_SEL)—Offset 74h ................................ 658
17.6.44 Shared Bus Control Register (SHARED_BUS)—Offset E0h.......................... 659
17.6.45 SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h ....................... 660
17.6.46 Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh .................... 661
17.6.47 Host Controller Version Register (HOST_CTRL_VER)—Offset FEh................ 661
18.0 High Speed UART ................................................................................................... 663
18.1 Signal Descriptions .......................................................................................... 663
18.2 Features ......................................................................................................... 664
18.2.1 UART Function...................................................................................... 664
18.2.2 Baud Rate Generator............................................................................. 664
18.3 Usage ............................................................................................................ 665
18.3.1 DMA Mode Operation............................................................................. 665
18.3.1.1 Receiver DMA ......................................................................... 665
18.3.1.2 Transmitter DMA ..................................................................... 666
18.3.2 FIFO Interrupt-Mode Operation............................................................... 666
18.3.2.1 Receiver Interrupt ................................................................... 666
18.3.2.2 Transmitter Interrupt............................................................... 666
18.3.3 FIFO Polled-Mode Operation ................................................................... 667
18.3.3.1 Receive Data Service ............................................................... 667
18.3.3.2 Transmit Data Service.............................................................. 667
18.3.4 Autoflow Control ................................................................................... 667
18.3.4.1 RTS (UART Output) ................................................................. 667
18.3.4.2 CTS (UART Input) ................................................................... 668
18.4 Register Map ................................................................................................... 668
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18.5
18.6
PCI Configuration Registers .............................................................................. 669
18.5.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 669
18.5.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 670
18.5.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 670
18.5.4 Status Register (STATUS)—Offset 6h ...................................................... 671
18.5.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 672
18.5.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 672
18.5.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 673
18.5.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 673
18.5.9 BIST (BIST)—Offset Fh ......................................................................... 673
18.5.10 Base Address Register (BAR0)—Offset 10h............................................. 674
18.5.11 Base Address Register (BAR1)—Offset 14h............................................. 674
18.5.12 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h .................... 675
18.5.13 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 675
18.5.14 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................. 676
18.5.15 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h............ 676
18.5.16 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 676
18.5.17 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 677
18.5.18 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 677
18.5.19 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 678
18.5.20 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 678
18.5.21 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 678
18.5.22 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h.......................... 679
18.5.23 Power Management Capabilities (PMC)—Offset 82h ................................. 679
18.5.24 Power Management Control/Status Register (PMCSR)—Offset 84h............. 680
18.5.25 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ... 681
18.5.26 Power Management Data Register (DATA_REGISTER)—Offset 87h ............ 681
18.5.27 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 681
18.5.28 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 682
18.5.29 Message Control (MESSAGE_CTRL)—Offset A2h...................................... 682
18.5.30 Message Address (MESSAGE_ADDR)—Offset A4h.................................... 682
18.5.31 Message Data (MESSAGE_DATA)—Offset A8h......................................... 683
18.5.32 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 683
18.5.33 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................................. 684
Memory Mapped Registers ................................................................................ 684
18.6.1 UART Registers .................................................................................... 684
18.6.1.1 Receive Buffer / Transmit Holding / Divisor Latch Low
(RBR_THR_DLL)—Offset 0h ...................................................... 685
18.6.1.2 Interrupt Enable / Divisor Latch High (IER_DLH)—Offset 4h.......... 685
18.6.1.3 Interrupt Identification / FIFO Control (IIR_FCR)—Offset 8h ......... 686
18.6.1.4 Line Control (LCR)—Offset Ch ................................................... 688
18.6.1.5 MODEM Control (MCR)—Offset 10h ........................................... 688
18.6.1.6 Line Status (LSR)—Offset 14h .................................................. 689
18.6.1.7 MODEM Status (MSR)—Offset 18h............................................. 691
18.6.1.8 Scratchpad (SCR)—Offset 1Ch .................................................. 692
18.6.1.9 UART Status (USR)—Offset 7Ch ................................................ 693
18.6.1.10 Halt Transmission (HTX)—Offset A4h....................................... 693
18.6.1.11 DMA Software Acknowledge (DMASA)—Offset A8h .................... 694
18.6.2 DMA Controller Registers....................................................................... 694
18.6.2.1 Channel 0 Source Address (SAR0)—Offset 0h ............................. 696
18.6.2.2 Channel 0 Destination Address (DAR0)—Offset 8h ....................... 696
18.6.2.3 Channel 0 Linked List Pointer (LLP0)—Offset 10h ........................ 697
18.6.2.4 Channel 0 Control LOWER (CTL0_L)—Offset 18h ......................... 697
18.6.2.5 Channel 0 Control UPPER (CTL0_U)—Offset 1Ch.......................... 699
18.6.2.6 Channel 0 Source Status (SSTAT0)—Offset 20h .......................... 700
18.6.2.7 Channel 0 Destination Status (DSTAT0)—Offset 28h .................... 700
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18.6.2.8 Channel 0 Source Status Address (SSTATAR0)—Offset 30h ........... 701
18.6.2.9 Channel 0 Destination Status Address (DSTATAR0)—Offset 38h..... 701
18.6.2.10 Channel 0 Configuration LOWER (CFG0_L)—Offset 40h .............. 702
18.6.2.11 Channel 0 configuration UPPER (CFG0_U)—Offset 44h ............... 703
18.6.2.12 Channel 0 Source Gather (SGR0)—Offset 48h ........................... 704
18.6.2.13 Channel 0 Destination Scatter (DSR0)—Offset 50h ..................... 705
18.6.2.14 Channel 1 Source Address (SAR1)—Offset 58h .......................... 705
18.6.2.15 Channel 1 Destination Address (DAR1)—Offset 60h .................... 706
18.6.2.16 Channel 1 Linked List Pointer (LLP1)—Offset 68h ....................... 706
18.6.2.17 Channel 1 Control LOWER (CTL1_L)—Offset 70h ........................ 707
18.6.2.18 Channel 1 Control UPPER (CTL1_U)—Offset 74h......................... 709
18.6.2.19 Channel 1 Source Status (SSTAT1)—Offset 78h ......................... 710
18.6.2.20 Channel 1 Destination Status (DSTAT1)—Offset 80h................... 710
18.6.2.21 Channel 1 Source Status Address (SSTATAR1)—Offset 88h ......... 711
18.6.2.22 Channel 1 Destination Status Address (DSTATAR1)—Offset 90h ... 711
18.6.2.23 Channel 1 Configuration LOWER (CFG1_L)—Offset 98h ............... 712
18.6.2.24 Channel 1 configuration UPPER (CFG1_U)—Offset 9Ch ................ 713
18.6.2.25 Channel 1 Source Gather (SGR1)—Offset A0h ........................... 714
18.6.2.26 Channel 1 Destination Scatter (DSR1)—Offset A8h ..................... 714
18.6.2.27 Raw Status for IntTfr Interrupt (RAW_TFR)—Offset 2C0h ............ 715
18.6.2.28 Raw Status for IntBlock Interrupt (RAW_BLOCK)—Offset 2C8h .... 715
18.6.2.29 Raw Status for IntSrcTran Interrupt (RAW_SRC_TRAN)—Offset
2D0h ..................................................................................... 716
18.6.2.30 Raw Status for IntDstTran Interrupt (RAW_DST_TRAN)—Offset
2D8h ..................................................................................... 716
18.6.2.31 Raw Status for IntErr Interrupt (RAW_ERR)—Offset 2E0h............ 717
18.6.2.32 Status for IntTfr Interrupt (STATUS_TFR)—Offset 2E8h .............. 717
18.6.2.33 Status for IntBlock Interrupt (STATUS_BLOCK)—Offset 2F0h ....... 718
18.6.2.34 Status for IntSrcTran Interrupt
(STATUS_SRC_TRAN)—Offset 2F8h.......................................... 718
18.6.2.35 Status for IntDstTran Interrupt
(STATUS_DST_TRAN)—Offset 300h.......................................... 719
18.6.2.36 Status for IntErr Interrupt (STATUS_ERR)—Offset 308h .............. 719
18.6.2.37 Mask for IntTfr Interrupt (MASK_TFR)—Offset 310h ................... 720
18.6.2.38 Mask for IntBlock Interrupt (MASK_BLOCK)—Offset 318h............ 720
18.6.2.39 Mask for IntSrcTran Interrupt (MASK_SRC_TRAN)—Offset 320h... 721
18.6.2.40 Mask for IntDstTran Interrupt (MASK_DST_TRAN)—Offset 328h... 722
18.6.2.41 Mask for IntErr Interrupt (MASK_ERR)—Offset 330h................... 722
18.6.2.42 Clear for IntTfr Interrupt (CLEAR_TFR)—Offset 338h .................. 723
18.6.2.43 Clear for IntBlock Interrupt (CLEAR_BLOCK)—Offset 340h........... 723
18.6.2.44 Clear for IntSrcTran Interrupt (CLEAR_SRC_TRAN)—Offset 348h.. 724
18.6.2.45 Clear for IntDstTran Interrupt (CLEAR_DST_TRAN)—Offset 350h . 724
18.6.2.46 Clear for IntErr Interrupt (CLEAR_ERR)—Offset 358h.................. 725
18.6.2.47 Combined Interrupt Status (STATUS_INT)—Offset 360h.............. 725
18.6.2.48 Source Software Transaction Request (REQ_SRC_REG)—Offset
368h ..................................................................................... 726
18.6.2.49 Destination Software Transaction Request register
(REQ_DST_REG)—Offset 370h .................................................. 726
18.6.2.50 Source Single Transaction Request (SGL_REQ_SRC_REG)—Offset
378h ..................................................................................... 727
18.6.2.51 Destination Single Software Transaction Request
(SGL_REQ_DST_REG)—Offset 380h ........................................... 728
18.6.2.52 Source Last Transaction Request (LST_SRC_REG)—Offset 388h ... 728
18.6.2.53 Destination Single Transaction Request (LST_DST_REG)—Offset
390h ..................................................................................... 729
18.6.2.54 DMA Configuration (DMA_CFG_REG)—Offset 398h ..................... 729
18.6.2.55 Channel Enable (CH_EN_REG)—Offset 3A0h .............................. 730
19.0 I2C* Controller/GPIO Controller ............................................................................ 731
19.1 I2C Controller.................................................................................................. 731
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19.2
19.3
19.4
19.5
19.1.1 Signal Descriptions ............................................................................... 731
19.1.2 Features ............................................................................................. 731
19.1.2.1 I2C* Protocol.......................................................................... 731
19.1.2.2 I2C* Modes of Operation .......................................................... 732
19.1.2.3 Functional Description ............................................................. 732
19.1.3 Use .................................................................................................... 737
19.1.3.1 Master Mode Operation............................................................ 737
19.1.3.2 Disabling I2C* Controller.......................................................... 737
19.1.4 References .......................................................................................... 738
GPIO Controller............................................................................................... 738
19.2.1 Signal Descriptions ............................................................................... 738
19.2.2 Features ............................................................................................. 738
Register Map .................................................................................................. 738
PCI Configuration Registers .............................................................................. 739
19.4.1 Vendor ID (VENDOR_ID)—Offset 0h ....................................................... 740
19.4.2 Device ID (DEVICE_ID)—Offset 2h ......................................................... 741
19.4.3 Command Register (COMMAND_REGISTER)—Offset 4h ............................. 741
19.4.4 Status Register (STATUS)—Offset 6h ...................................................... 742
19.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h ................. 742
19.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ...................................... 743
19.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ........................................... 743
19.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 744
19.4.9 BIST (BIST)—Offset Fh ......................................................................... 744
19.4.10 Base Address Register (BAR0)—Offset 10h............................................. 745
19.4.11 Base Address Register (BAR1)—Offset 14h............................................. 745
19.4.12 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h .................... 746
19.4.13 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 746
19.4.14 Subsystem ID (SUB_SYS_ID)—Offset 2Eh ............................................. 747
19.4.15 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h............ 747
19.4.16 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 747
19.4.17 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 748
19.4.18 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 748
19.4.19 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 749
19.4.20 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 749
19.4.21 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 749
19.4.22 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h.......................... 750
19.4.23 Power Management Capabilities (PMC)—Offset 82h ................................. 750
19.4.24 Power Management Control/Status Register (PMCSR)—Offset 84h............. 751
19.4.25 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h ... 752
19.4.26 Power Management Data Register (DATA_REGISTER)—Offset 87h ............ 752
19.4.27 Capability ID (MSI_CAP_ID)—Offset A0h ............................................... 752
19.4.28 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 753
19.4.29 Message Control (MESSAGE_CTRL)—Offset A2h...................................... 753
19.4.30 Message Address (MESSAGE_ADDR)—Offset A4h.................................... 754
19.4.31 Message Data (MESSAGE_DATA)—Offset A8h......................................... 754
19.4.32 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 754
19.4.33 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h................................. 755
Memory Mapped Registers ................................................................................ 755
19.5.1 I2C* Controller Memory Mapped Registers............................................... 755
19.5.1.1 Control Register (IC_CON)—Offset 0h........................................ 756
19.5.1.2 Master Target Address (IC_TAR)—Offset 4h................................ 757
19.5.1.3 Data Buffer and Command (IC_DATA_CMD)—Offset 10h .............. 758
19.5.1.4 Standard Speed Clock SCL High Count (IC_SS_SCL_HCNT)—Offset
14h....................................................................................... 759
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19.5.1.5 Standard Speed Clock SCL Low Count (IC_SS_SCL_LCNT)—Offset
18h ....................................................................................... 760
19.5.1.6 Fast Speed Clock SCL High Count (IC_FS_SCL_HCNT)—Offset 1Ch 760
19.5.1.7 Fast Speed Clock SCL Low Count (IC_FS_SCL_LCNT)—Offset 20h .. 761
19.5.1.8 Interrupt Status (IC_INTR_STAT)—Offset 2Ch............................. 761
19.5.1.9 Interrupt Mask (IC_INTR_MASK)—Offset 30h .............................. 763
19.5.1.10 Raw Interrupt Status (IC_RAW_INTR_STAT)—Offset 34h ........... 764
19.5.1.11 Receive FIFO Threshold Level (IC_RX_TL)—Offset 38h ............... 766
19.5.1.12 Transmit FIFO Threshold Level (IC_TX_TL)—Offset 3Ch.............. 766
19.5.1.13 Clear Combined and Individual Interrupt (IC_CLR_INTR)—Offset
40h ....................................................................................... 767
19.5.1.14 Clear RX_UNDER Interrupt (IC_CLR_RX_UNDER)—Offset 44h ..... 767
19.5.1.15 Clear RX_OVER Interrupt (IC_CLR_RX_OVER)—Offset 48h ......... 768
19.5.1.16 Clear TX_OVER Interrupt (IC_CLR_TX_OVER)—Offset 4Ch.......... 768
19.5.1.17 Clear RD_REQ Interrupt (IC_CLR_RD_REQ)—Offset 50h............. 769
19.5.1.18 Clear TX_ABRT Interrupt (IC_CLR_TX_ABRT)—Offset 54h........... 769
19.5.1.19 Clear ACTIVITY Interrupt (IC_CLR_ACTIVITY)—Offset 5Ch.......... 770
19.5.1.20 Clear STOP_DET Interrupt (IC_CLR_STOP_DET)—Offset 60h....... 770
19.5.1.21 Clear START_DET Interrupt (IC_CLR_START_DET)—Offset 64h ... 771
19.5.1.22 Enable (IC_ENABLE)—Offset 6Ch ............................................ 771
19.5.1.23 Status (IC_STATUS)—Offset 70h............................................. 772
19.5.1.24 Transmit FIFO Level (IC_TXFLR)—Offset 74h ............................ 773
19.5.1.25 Receive FIFO Level (IC_RXFLR)—Offset 78h.............................. 774
19.5.1.26 SDA Hold (IC_SDA_HOLD)—Offset 7Ch .................................... 774
19.5.1.27 Transmit Abort Source (IC_TX_ABRT_SOURCE)—Offset 80h ....... 775
19.5.1.28 Enable Status (IC_ENABLE_STATUS)—Offset 9Ch...................... 776
19.5.1.29 SS and FS Spike Suppression Limit (IC_FS_SPKLEN)—Offset A0h 777
19.5.2 GPIO Controller Memory Mapped Registers............................................... 777
19.5.2.1 Port A Data (GPIO_SWPORTA_DR)—Offset 0h ............................. 778
19.5.2.2 Port A Data Direction (GPIO_SWPORTA_DDR)—Offset 4h.............. 778
19.5.2.3 Interrupt Enable (GPIO_INTEN)—Offset 30h ............................... 779
19.5.2.4 Interrupt Mask (GPIO_INTMASK)—Offset 34h ............................. 779
19.5.2.5 Interrupt Type (GPIO_INTTYPE_LEVEL)—Offset 38h ..................... 780
19.5.2.6 Interrupt Polarity (GPIO_INT_POLARITY)—Offset 3Ch .................. 781
19.5.2.7 Interrupt Status (GPIO_INTSTATUS)—Offset 40h......................... 781
19.5.2.8 Raw Interrupt Status (GPIO_RAW_INTSTATUS)—Offset 44h.......... 782
19.5.2.9 Debounce Enable (GPIO_DEBOUNCE)—Offset 48h ....................... 782
19.5.2.10 Clear Interrupt (GPIO_PORTA_EOI)—Offset 4Ch ........................ 783
19.5.2.11 Port A External Port (GPIO_EXT_PORTA)—Offset 50h.................. 784
19.5.2.12 Synchronization Level (GPIO_LS_SYNC)—Offset 60h .................. 784
20.0 SPI Interface ........................................................................................................ 787
20.1 Signal Descriptions .......................................................................................... 787
20.2 Features ......................................................................................................... 787
20.2.1 SPI Controller....................................................................................... 787
20.2.1.1 Processor-Initiated Data Transfer .............................................. 788
20.2.1.2 Data Format ........................................................................... 788
20.2.1.3 FIFO Operation ....................................................................... 789
20.2.1.4 Baud Rate Generation .............................................................. 789
20.3 Register Map ................................................................................................... 791
20.4 PCI Configuration Registers ............................................................................... 792
20.4.1 Vendor ID (VENDOR_ID)—Offset 0h ........................................................ 792
20.4.2 Device ID (DEVICE_ID)—Offset 2h .......................................................... 793
20.4.3 Command Register (COMMAND_REGISTER)—Offset 4h .............................. 793
20.4.4 Status Register (STATUS)—Offset 6h....................................................... 794
20.4.5 Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h .................. 795
20.4.6 Cache Line Size (CACHE_LINE_SIZE)—Offset Ch ....................................... 795
20.4.7 Latency Timer (LATENCY_TIMER)—Offset Dh ............................................ 796
20.4.8 Header Type (HEADER_TYPE)—Offset Eh ................................................. 796
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20.5
20.4.9 BIST (BIST)—Offset Fh ......................................................................... 796
20.4.10 Base Address Register (BAR0)—Offset 10h ............................................. 797
20.4.11 Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h..................... 798
20.4.12 Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch ..................... 798
20.4.13 Subsystem ID (SUB_SYS_ID)—Offset 2Eh.............................................. 798
20.4.14 Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h ............ 799
20.4.15 Capabilities Pointer (CAP_POINTER)—Offset 34h ..................................... 799
20.4.16 Interrupt Line Register (INTR_LINE)—Offset 3Ch .................................... 799
20.4.17 Interrupt Pin Register (INTR_PIN)—Offset 3Dh ....................................... 800
20.4.18 MIN_GNT (MIN_GNT)—Offset 3Eh......................................................... 800
20.4.19 MAX_LAT (MAX_LAT)—Offset 3Fh ......................................................... 801
20.4.20 Capability ID (PM_CAP_ID)—Offset 80h ................................................. 801
20.4.21 Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h .......................... 801
20.4.22 Power Management Capabilities (PMC)—Offset 82h ................................. 802
20.4.23 Power Management Control/Status Register (PMCSR)—Offset 84h ............. 802
20.4.24 PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h.... 803
20.4.25 Power Management Data Register (DATA_REGISTER)—Offset 87h............. 803
20.4.26 Capability ID (MSI_CAP_ID)—Offset A0h................................................ 804
20.4.27 Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h ........................ 804
20.4.28 Message Control (MESSAGE_CTRL)—Offset A2h ...................................... 804
20.4.29 Message Address (MESSAGE_ADDR)—Offset A4h .................................... 805
20.4.30 Message Data (MESSAGE_DATA)—Offset A8h......................................... 805
20.4.31 Mask Bits for MSI (PER_VEC_MASK)—Offset ACh .................................... 806
20.4.32 Pending Bits for MSI (PER_VEC_PEND)—Offset B0h ................................. 806
Memory Mapped Registers ................................................................................ 807
20.5.1 SPI Control Register 0 (SSCR0)—Offset 0h .............................................. 807
20.5.2 SPI Control Register 1 (SSCR1)—Offset 4h .............................................. 808
20.5.3 SPI Status Register (SSSR)—Offset 8h .................................................... 810
20.5.4 SPI Data Register (SSDR)—Offset 10h .................................................... 811
20.5.5 DDS Clock Rate Register (DDS_RATE)—Offset 28h.................................... 812
21.0 Legacy Bridge........................................................................................................ 815
21.1 Features ........................................................................................................ 815
21.2 Register Map .................................................................................................. 816
21.3 PCI Configuration Registers .............................................................................. 817
21.3.1 PCI Device ID and Vendor ID Fields (PCI_DEVICE_VENDOR)—Offset 0h....... 818
21.3.2 PCI Status and Command Fields (PCI_STATUS_COMMAND)—Offset 4h ........ 818
21.3.3 PCI Class Code and Revision ID Fields (PCI_CLASS_REVISION)—Offset 8h ... 819
21.3.4 PCI Miscellaneous Fields (PCI_MISC)—Offset Ch ....................................... 819
21.3.5 PCI Subsystem ID and Subsystem Vendor ID Fields
(PCI_SUBSYSTEM)—Offset 2Ch .............................................................. 820
21.3.6 GPIO Base Address (GBA)—Offset 44h .................................................... 821
21.3.7 PM1_BLK Base Address (PM1BLK)—Offset 48h ......................................... 821
21.3.8 GPE0_BLK Base Address (GPE0BLK)—Offset 4Ch ...................................... 821
21.3.9 ACPI Control (ACTL)—Offset 58h ............................................................ 822
21.3.10 PIRQA, PIRQB, PIRQC and PIRQD Routing Control (PABCDRC)—Offset 60h. 822
21.3.11 PIRQE, PIRQF, PIRQG and PIRQH Routing Control (PEFGHRC)—Offset 64h . 824
21.3.12 Watch Dog Timer Base Address (WDTBA)—Offset 84h ............................. 824
21.3.13 BIOS Decode Enable (BCE)—Offset D4h ................................................ 825
21.3.14 BIOS Control (BC)—Offset D8h............................................................. 826
21.3.15 Root Complex Base Address (RCBA)—Offset F0h..................................... 827
21.4 Memory Mapped Registers ................................................................................ 827
21.4.1 Root Complex Register Block ................................................................. 827
21.4.1.1 Root Complex Topology Capabilities List (RCTCL)—Offset 0h......... 828
21.4.1.2 Element Self Description (ESD)—Offset 4h ................................. 828
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21.5
21.6
21.7
21.4.1.3 Interrupt Queue Agent 0 (IRQAGENT0)—Offset 3140h.................. 829
21.4.1.4 Interrupt Queue Agent 1 (IRQAGENT1)—Offset 3142h.................. 829
21.4.1.5 Interrupt Queue Agent 2 (IRQAGENT2)—Offset 3144h.................. 830
21.4.1.6 Interrupt Queue Agent 3 (IRQAGENT3)—Offset 3146h.................. 830
21.4.1.7 RTC Configuration (RC)—Offset 3400h ....................................... 831
IO Registers.................................................................................................... 832
21.5.1 Fixed IO Registers ................................................................................ 832
21.5.1.1 NMI Status and Control Register (NSC)—Offset 61h ..................... 832
21.5.1.2 NMI Enable and RTC Index Register (NMIE)—Offset 70h ............... 833
21.5.1.3 Software SMI Control Port (SWSMICTL)—Offset B2h .................... 833
21.5.1.4 Software SMI Status Port (SWSMISTS)—Offset B3h ..................... 834
21.5.1.5 Reset Control Register (RSTC)—Offset CF9h................................ 834
21.5.2 ACPI GPE0 Block................................................................................... 835
21.5.2.1 GPE0 Status Register (GPE0STS)—Offset 0h ............................... 835
21.5.2.2 GPE0 Enable Register (GPE0EN)—Offset 4h................................. 836
21.5.2.3 SMI Enable Register (SMIEN)—Offset 10h................................... 837
21.5.2.4 SMI Status Register (SMISTS)—Offset 14h ................................. 838
21.5.2.5 General Purpose Event Control Register (GPEC)—Offset 18h ......... 839
21.5.2.6 Power Management Configuration Core Well Register
(PMCW)—Offset 28h ................................................................ 839
21.5.2.7 Power Management Configuration Suspend Well Register (PMSW)—
Offset 2Ch.............................................................................. 840
21.5.2.8 Power Management Configuration RTC Well Register
(PMRW)—Offset 30h ................................................................ 841
21.5.3 ACPI PM1 Block .................................................................................... 841
21.5.3.1 PM1 Status Register (PM1S)—Offset 0h ...................................... 841
21.5.3.2 PM1 Enable Register (PM1E)—Offset 2h...................................... 842
21.5.3.3 PM1 Control Register (PM1C)—Offset 4h ..................................... 843
21.5.3.4 Power Management 1 Timer Register (PM1T)—Offset 8h ............... 844
Legacy GPIO ................................................................................................... 845
21.6.1 Signal Descriptions ............................................................................... 845
21.6.2 Features .............................................................................................. 845
21.6.3 Use..................................................................................................... 845
21.6.4 Register Map ........................................................................................ 846
21.6.5 IO Mapped Registers ............................................................................. 846
21.6.5.1 Core Well GPIO Enable (CGEN)—Offset 0h .................................. 847
21.6.5.2 Core Well GPIO Input/Output Select (CGIO)—Offset 4h ................ 847
21.6.5.3 Core Well GPIO Level for Input or Output (CGLVL)—Offset 8h........ 848
21.6.5.4 Core Well GPIO Trigger Positive Edge Enable (CGTPE)—Offset Ch .. 848
21.6.5.5 Core Well GPIO Trigger Negative Edge Enable (CGTNE)—Offset
10h ....................................................................................... 849
21.6.5.6 Core Well GPIO GPE Enable (CGGPE)—Offset 14h ........................ 849
21.6.5.7 Core Well GPIO SMI Enable (CGSMI)—Offset 18h ........................ 850
21.6.5.8 Core Well GPIO Trigger Status (CGTS)—Offset 1Ch ...................... 850
21.6.5.9 Resume Well GPIO Enable (RGEN)—Offset 20h............................ 851
21.6.5.10 Resume Well GPIO Input/Output Select (RGIO)—Offset 24h ........ 851
21.6.5.11 Resume Well GPIO Level for Input or Output (RGLVL)—Offset 28h 852
21.6.5.12 Resume Well GPIO Trigger Positive Edge Enable (RGTPE)—Offset
2Ch ....................................................................................... 852
21.6.5.13 Resume Well GPIO Trigger Negative Edge Enable (RGTNE)—Offset
30h ....................................................................................... 852
21.6.5.14 Resume Well GPIO GPE Enable (RGGPE)—Offset 34h .................. 853
21.6.5.15 Resume Well GPIO SMI Enable (RGSMI)—Offset 38h .................. 854
21.6.5.16 Resume Well GPIO Trigger Status (RGTS)—Offset 3Ch................ 854
21.6.5.17 Core Well GPIO NMI Enable (CGNMIEN)—Offset 40h................... 855
21.6.5.18 Resume Well GPIO NMI Enable (RGNMIEN)—Offset 44h .............. 855
Legacy SPI Controller ....................................................................................... 856
21.7.1 Signal Descriptions ............................................................................... 856
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21.8
21.9
21.7.2 Features ............................................................................................. 856
21.7.3 Register Map ....................................................................................... 856
21.7.4 Legacy SPI Host Interface Registers........................................................ 857
21.7.4.1 SPI Status (SPISTS)—Offset 3020h ........................................... 859
21.7.4.2 SPI Control (SPICTL)—Offset 3022h .......................................... 859
21.7.4.3 SPI Address (SPIADDR)—Offset 3024h ...................................... 860
21.7.4.4 SPI Data 0 - Lower 32 Bits (SPID0_1)—Offset 3028h................... 861
21.7.4.5 SPI Data 0 - Upper 32 Bits (SPID0_2)—Offset 302Ch................... 861
21.7.4.6 SPI Data 1 - Lower 32 Bits (SPID1_1)—Offset 3030h................... 862
21.7.4.7 SPI Data 1 - Upper 32 Bits (SPID1_2)—Offset 3034h ................... 862
21.7.4.8 SPI Data 2 - Lower 32 Bits (SPID2_1)—Offset 3038h................... 862
21.7.4.9 SPI Data 2 - Upper 32 Bits (SPID2_2)—Offset 303Ch................... 863
21.7.4.10 SPI Data 3 - Lower 32 Bits (SPID3_1)—Offset 3040h ................. 863
21.7.4.11 SPI Data 3 - Upper 32 Bits (SPID3_2)—Offset 3044h ................. 863
21.7.4.12 SPI Data 4 - Lower 32 Bits (SPID4_1)—Offset 3048h ................. 864
21.7.4.13 SPI Data 4 - Upper 32 Bits (SPID4_2)—Offset 304Ch ................. 864
21.7.4.14 SPI Data 5 - Lower 32 Bits (SPID5_1)—Offset 3050h ................. 865
21.7.4.15 SPI Data 5 - Upper 32 Bits (SPID5_2)—Offset 3054h ................. 865
21.7.4.16 SPI Data 6 - Lower 32 Bits (SPID6_1)—Offset 3058h ................. 865
21.7.4.17 SPI Data 6 - Upper 32 Bits (SPID6_2)—Offset 305Ch ................. 866
21.7.4.18 SPI Data 7 - Lower 32 Bits (SPID7_1)—Offset 3060h ................. 866
21.7.4.19 SPI Data 7 - Upper 32 Bits (SPID7_2)—Offset 3064h ................. 866
21.7.4.20 BIOS Base Address (BBAR)—Offset 3070h ................................ 867
21.7.4.21 Prefix Opcode Configuration (PREOP)—Offset 3074h .................. 867
21.7.4.22 Opcode Type Configuration (OPTYPE)—Offset 3076h .................. 868
21.7.4.23 Opcode Menu Configuration - Lower 32 Bits (OPMENU_1)—Offset
3078h ................................................................................... 869
21.7.4.24 Opcode Menu Configuration - Upper 32 Bits (OPMENU_2)—Offset
307Ch ................................................................................... 869
21.7.4.25 Protected BIOS Range 0 (PBR0)—Offset 3080h ......................... 870
21.7.4.26 Protected BIOS Range 1 (PBR1)—Offset 3084h ......................... 871
21.7.4.27 Protected BIOS Range 2 (PBR2)—Offset 3088h ......................... 871
8254 Programmable Interval Timer.................................................................... 873
21.8.1 Features ............................................................................................. 873
21.8.1.1 Counter 0, System Timer ......................................................... 873
21.8.1.2 Counter 1, Refresh Request Signal ............................................ 873
21.8.1.3 Counter 2, Speaker Tone ......................................................... 873
21.8.2 Use .................................................................................................... 873
21.8.2.1 Timer Programming ................................................................ 873
21.8.2.2 Reading from the Interval Timer ............................................... 874
21.8.3 Register Map ....................................................................................... 875
21.8.4 Timer I/O Registers .............................................................................. 876
21.8.4.1 Counter 0 Interval Time Status Byte Format (C0TS)—Offset 40h ... 877
21.8.4.2 Counter 1 Interval Time Status Byte Format (C1TS)—Offset 41h ... 877
21.8.4.3 Counter 2 Interval Time Status Byte Format (C2TS)—Offset 42h ... 878
21.8.4.4 Timer Control Word Register (TCW)—Offset 43h ......................... 879
21.8.4.5 Counter 0 Counter Access Port Register (C0AP)—Offset 50h ......... 879
21.8.4.6 Counter 1 Counter Access Port Register (C1AP)—Offset 51h ......... 880
21.8.4.7 Counter 2 Counter Access Port Register (C2AP)—Offset 52h ......... 880
High Precision Event Timer (HPET)..................................................................... 880
21.9.1 Features ............................................................................................. 881
21.9.1.1 Non-Periodic Mode - All Timers ................................................. 881
21.9.1.2 Periodic Mode - Timer 0 Only.................................................... 881
21.9.1.3 Interrupts .............................................................................. 882
21.9.2 Register Map ....................................................................................... 882
21.9.3 Memory Mapped Registers..................................................................... 883
21.9.3.1 General Capabilities and ID Register - Lower 32 Bits
(GCID_1)—Offset 0h ............................................................... 884
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21.9.3.2 General Capabilities and ID Register - Upper 32 Bits
(GCID_2)—Offset 4h................................................................ 885
21.9.3.3 General Configuration (GC)—Offset 10h ..................................... 885
21.9.3.4 General Interrupt Status Register (GIS)—Offset 20h .................... 885
21.9.3.5 Main Counter Value Register - Lower 32 Bits (MCV_1)—Offset F0h . 886
21.9.3.6 Main Counter Value Register - Upper 32 Bits (MCV_2)—Offset F4h . 886
21.9.3.7 Timer 0 Config and Capabilities Register - Lower 32 Bits
(T0C_1)—Offset 100h .............................................................. 887
21.9.3.8 Timer 0 Config and Capabilities Register - Upper 32 Bits
(T0C_2)—Offset 104h .............................................................. 888
21.9.3.9 Timer 0 Comparator Value Register - Lower 32 Bits
(T0CV_1)—Offset 108h ............................................................ 888
21.9.3.10 Timer 0 Comparator Value Register - Upper 32 Bits
(T0CV_2)—Offset 10Ch ............................................................ 888
21.9.3.11 Timer 1 Config and Capabilities Register - Lower 32 Bits (T1C_1)—
Offset 120h ............................................................................ 889
21.9.3.12 Timer 1 Config and Capabilities Register - Upper 32 Bits (T1C_2)—
Offset 124h ............................................................................ 890
21.9.3.13 Timer 1 Comparator Value Register (T1CV_1)—Offset 128h......... 890
21.9.3.14 Timer 2 Config and Capabilities Register - Lower 32 Bits (T2C_1)—
Offset 140h ............................................................................ 890
21.9.3.15 Timer 2 Config and Capabilities Register - Upper 32 Bits (T2C_2)—
Offset 144h ............................................................................ 891
21.9.3.16 Timer 2 Comparator Value Register (T2CV_1)—Offset 148h......... 892
21.9.4 References........................................................................................... 892
21.10 Real Time Clock (RTC)...................................................................................... 892
21.10.1 Signal Descriptions .............................................................................. 892
21.10.2 Features ............................................................................................ 893
21.10.2.1 Update Cycles ....................................................................... 893
21.10.2.2 Interrupts............................................................................. 893
21.10.2.3 Lockable RAM Ranges ............................................................ 893
21.10.3Register Map ........................................................................................ 894
21.10.4I/O Registers ....................................................................................... 894
21.10.5Indexed Registers ................................................................................. 895
21.10.5.1 Offset 0Ah: Register A............................................................ 896
21.10.5.2 Offset 0Bh: Register B - General Configuration .......................... 896
21.10.5.3 Offset 0Ch: Register C - Flag Register ...................................... 897
21.10.5.4 Offset 0Dh: Register D - Flag Register ...................................... 898
21.10.6References........................................................................................... 898
21.11 Interrupt Decoding & Routing ............................................................................ 898
21.11.1Features .............................................................................................. 898
21.11.1.1 Interrupt Decoder .................................................................. 898
21.11.1.2 Interrupt Router .................................................................... 899
21.12 8259 Programmable Interrupt Controllers (PIC) ................................................... 899
21.12.1Features .............................................................................................. 900
21.12.1.1 Interrupt Handling ................................................................. 900
21.12.1.2 Initialization Command Words (ICWx) ...................................... 902
21.12.1.3 Operation Command Words (OCW) .......................................... 903
21.12.1.4 Modes of Operation................................................................ 903
21.12.1.5 Masking Interrupts ................................................................ 905
21.12.1.6 Steering of PCI Interrupts....................................................... 905
21.12.2Register Map ........................................................................................ 905
21.12.3I/O Registers ....................................................................................... 906
21.12.3.1 Master Initialization Command Word 1 (MICW1)—Offset 20h ....... 908
21.12.3.2 Master Initialization Command Word 2 (MICW2)—Offset 21h ....... 909
21.12.3.3 Master Operational Control Word 2 (MOCW2)—Offset 24h ........... 909
21.12.3.4 Master Initialization Command Word 3 (MICW3)—Offset 25h ....... 910
21.12.3.5 Master Operational Control Word 3 (MOCW3)—Offset 28h ........... 910
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21.12.3.6 Master Initialization Command Word 4 (MICW4)—Offset 29h ...... 911
21.12.3.7 Master Operational Control Word 1 (MOCW1)—Offset 2Dh .......... 912
21.12.3.8 Slave Initialization Command Word 1 (SICW1)—Offset A0h ........ 912
21.12.3.9 Slave Initialization Command Word 2 (SICW2)—Offset A1h ........ 913
21.12.3.10 Slave Operational Control Word 2 (SoCW2)—Offset A4h............ 913
21.12.3.11 Slave Initialization Command Word 3 (SICW3)—Offset A5h ....... 914
21.12.3.12 Slave Operational Control Word 3 (SoCW3)—Offset A8h............ 914
21.12.3.13 Slave Initialization Command Word 4 (SICW4)—Offset A9h ....... 915
21.12.3.14 Slave Operational Control Word 1 (SoCW1)—Offset ADh ........... 916
21.12.3.15 Master Edge/Level Control (ELCR1)—Offset 4D0h..................... 916
21.12.3.16 Slave Edge/Level Control (ELCR2)—Offset 4D1h ...................... 916
21.13 I/O APIC ........................................................................................................ 918
21.13.1Features ............................................................................................. 918
21.13.2Use .................................................................................................... 919
21.13.3Unsupported Modes .............................................................................. 919
21.13.4Register Map ....................................................................................... 920
21.13.5Memory Mapped Registers..................................................................... 920
21.13.5.1 Index Register (IDX)—Offset FEC00000h .................................. 921
21.13.5.2 Window Register (WDW)—Offset FEC00010h............................. 921
21.13.5.3 End of Interrupt Register (EOI)—Offset FEC00040h.................... 921
21.13.6Index Registers.................................................................................... 922
21.13.6.1 Identification Register (ID)—Offset 0h ..................................... 922
21.13.6.2 Version Register (VS)—Offset 1h ............................................. 923
21.13.6.3 Redirection Table Entry Lower (RTE[0-23]L)—Offset 10h - 3Eh.... 923
21.13.6.4 Redirection Table Entry Upper (RTE[0-23]U)—Offset 11h - 3Fh ... 924
21.14 Watchdog Timer.............................................................................................. 926
21.14.1Features ............................................................................................. 926
21.14.2Use .................................................................................................... 926
21.14.3Register Map ....................................................................................... 927
21.14.4I/O Mapped Registers ........................................................................... 927
21.14.4.1 Preload Value 1 Register 0 (PV1R0)—Offset 0h ......................... 928
21.14.4.2 Preload Value 1 Register 1 (PV1R1)—Offset 1h ......................... 928
21.14.4.3 Preload Value 1 Register 2 (PV1R2)—Offset 2h ......................... 929
21.14.4.4 Preload Value 2 Register 0 (PV2R0)—Offset 4h ......................... 929
21.14.4.5 Preload Value 2 Register 1 (PV2R1)—Offset 5h ......................... 930
21.14.4.6 Preload Value 2 Register 2 (PV2R2)—Offset 6h ......................... 930
21.14.4.7 Reload Register 0 (RR0)—Offset Ch ......................................... 930
21.14.4.8 Reload Register 1 (RR1)—Offset Dh......................................... 931
21.14.4.9 WDT Configuration Register (WDTCR)—Offset 10h .................... 931
21.14.4.10 WDT Lock Register (WDTLR)—Offset 18h ................................ 932
22.0 Debug Port and JTAG/TAP ..................................................................................... 935
22.1 Signal Descriptions .......................................................................................... 935
22.2 Features ........................................................................................................ 936
22.2.1 OpenOCD ............................................................................................ 936
Figures
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2
3
4
5
6
7
Block Diagram ......................................................................................................... 38
Intel® Quark™ SoC X1000 PCI View............................................................................ 43
Signals In Default System Pin List .............................................................................. 46
Intel® Quark™ SoC X1000 Package Dimensions............................................................ 59
PCI Express Transmitter Eye...................................................................................... 76
PCI Express Receiver Eye .......................................................................................... 76
USB Rise and Fall Time ............................................................................................. 78
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USB Jitter................................................................................................................79
USB EOP Width ........................................................................................................79
SPI Interface Timing .................................................................................................81
SDIO Interface Timing ..............................................................................................82
Measurement Points for Differential Clocks...................................................................84
Physical Address Space - Low DRAM & MMIO................................................................92
Physical Address Space - MMIO ..................................................................................93
Physical Address Space - DOS DRAM...........................................................................94
Physical Address Space - SMM Range ..........................................................................95
Bus 0 PCI Devices and Functions ................................................................................98
Message Bus with PCI Space ......................................................................................99
SoC Platform Clocking ............................................................................................. 102
RTC Power Well Timing Diagrams ............................................................................. 115
Power Up Sequence ................................................................................................ 117
Power-Up Sequence without G2/G3........................................................................... 118
eSRAM 4KB Page Mapping ....................................................................................... 128
eSRAM 512KB Page Mapping.................................................................................... 129
Intel® Quark™ SoC X1000 Host Bridge Register Map ................................................... 132
Register Map.......................................................................................................... 236
PCI Express Register Map ........................................................................................ 264
Ethernet Register Map............................................................................................. 311
Transmit Descriptor Fields ....................................................................................... 422
Transmit Descriptor Fetch (Read) ............................................................................. 423
Receive Descriptor Fields ......................................................................................... 427
USB Register Map................................................................................................... 437
SD Memory Card Bus Topology................................................................................. 593
SDIO Card Bus Topology ......................................................................................... 593
eMMC Interface ...................................................................................................... 594
SDIO/SD/eMMC Register Map................................................................................... 596
UART Data Transfer Flow ......................................................................................... 664
HSUART Register Map ............................................................................................. 668
Data Transfer on the I2C* Bus.................................................................................. 733
START and STOP Conditions..................................................................................... 733
7-Bit Address Format .............................................................................................. 734
10-bit Address Format ............................................................................................ 734
Master Transmitter Protocol ..................................................................................... 735
Master Receiver Protocol ......................................................................................... 736
START Byte Transfer ............................................................................................... 736
I2C*/GPIO Register Map.......................................................................................... 739
Generic SPI Waveform ............................................................................................ 788
SPI Register Map .................................................................................................... 791
Legacy Bridge Register Map ..................................................................................... 817
Legacy GPIO Register Map ....................................................................................... 846
Legacy SPI Register Map ......................................................................................... 857
8254 Timers Register Map ....................................................................................... 876
HPET Register Map ................................................................................................. 883
RTC Register Map ................................................................................................... 894
8259 Register Map.................................................................................................. 906
Detailed I/O APIC Block Diagram .............................................................................. 918
MSI Address and Data............................................................................................. 919
I/O APIC Register Map ............................................................................................ 920
Watchdog Timer Register Map .................................................................................. 927
Tables
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Industry Specifications.............................................................................................. 37
Component Identification .......................................................................................... 42
Intel® Quark™ SoC X1000 Device ID .......................................................................... 44
I/O Power Well Definitions......................................................................................... 47
Buffer Type Definitions ............................................................................................. 47
Default Buffer State Definitions .................................................................................. 47
System Memory Signals............................................................................................ 48
PCI Express* 2.0 Signals........................................................................................... 48
Ethernet Interface Signals ......................................................................................... 49
USB 2.0 Interface Signals ......................................................................................... 49
Integrated Clock Interface Signals.............................................................................. 50
SD/SDIO/MMC Signals .............................................................................................. 50
High Speed UART Signals .......................................................................................... 51
I2C* Signals ............................................................................................................ 51
Legacy SPI Signals ................................................................................................... 52
SPI Signals ............................................................................................................. 52
Real Time Clock (RTC) Interface Signals...................................................................... 53
Power Management Interface Signals.......................................................................... 53
JTAG and Debug Interface Signals .............................................................................. 54
Legacy Interface Signals ........................................................................................... 54
General Purpose I/O Signals ..................................................................................... 54
Power and Ground Pins ............................................................................................. 55
Hardware Straps ...................................................................................................... 57
Alphabetical Ball Listing ............................................................................................ 60
Alphabetical Signal Listing ......................................................................................... 64
Intel® Quark™ SoC X1000 Absolute Maximum Voltage Ratings ....................................... 69
Power Supply Rail Ranges ......................................................................................... 70
Maximum Supply Current: ICC Max ............................................................................ 71
Configurable IO (CFIO) Bi-directional Signal Groupings ................................................. 72
CFIO DC Characteristics ............................................................................................ 73
CFIO AC Characteristics ............................................................................................ 73
RTC DC Characteristics ............................................................................................. 74
PCI Express* 2.0 Differential Signal DC Characteristics ................................................. 74
PCI Express* 2.0 Interface Timings ............................................................................ 75
USB 2.0 Differential Signal DC Characteristics .............................................................. 77
USB 2.0 Interface Timings......................................................................................... 77
Legacy SPI Interface Timings (20 MHz) ....................................................................... 79
SPI0/1 Interface Timings (25 MHz)............................................................................. 80
SDIO Timing ........................................................................................................... 81
Reference Clocks AC Characteristics ........................................................................... 82
Fixed I/O Register Access Method Example (NSC Register) ............................................ 85
Fixed Memory Mapped Register Access Method Example (IDX Register)........................... 85
Referenced I/O Register Access Method Example (PM1S Register) .................................. 86
Memory Mapped Register Access Method Example (ESD Register) .................................. 86
PCI Register Access Method Example (PCI_DEVICE_VENDOR Register)............................ 86
PCI CONFIG_ADDRESS Register (I/O PORT CF8h) Mapping ............................................ 87
PCI Configuration Memory Bar Mapping....................................................................... 87
MCR Description ...................................................................................................... 88
MCRX Description..................................................................................................... 88
Register Access Types and Definitions......................................................................... 89
Fixed Memory Ranges in the Legacy Bridge ................................................................. 95
Fixed I/O Ranges in the Legacy Bridge ........................................................................ 96
Movable I/O Ranges Decoded by PCI Devices on the I/O Fabric ...................................... 96
PCI Devices and Functions......................................................................................... 97
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99
100
101
102
103
104
105
106
107
108
109
110
Message Types.........................................................................................................99
Intel® Quark™ SoC X1000 Clock Inputs ..................................................................... 103
Intel® Quark™ SoC X1000 Clock Outputs ................................................................... 103
Power Management ................................................................................................ 105
General Power States for System.............................................................................. 107
ACPI PM State Transition Rules................................................................................. 107
Processor Core/ States Support ................................................................................ 108
Main Memory States ............................................................................................... 108
PCIe* States.......................................................................................................... 108
G, S and C State Combinations................................................................................. 109
RTC Power Well Timing Parameters ........................................................................... 115
S4/S5 to S0 Timing Parameters................................................................................ 119
Intel® Quark™ SoC X1000 S3 Wake Events ................................................................ 121
SoC Reset Events ................................................................................................... 121
Thermal Sensor Signals ........................................................................................... 123
Summary of PCI Configuration Registers—0/0/0 ......................................................... 132
Summary of I/O Registers—PMBA............................................................................. 138
Summary of Message Bus Registers—0x00 ................................................................ 140
Summary of Message Bus Registers—0x03 ................................................................ 145
Summary of Message Bus Registers—0x04 ................................................................ 174
Summary of Message Bus Registers—0x05 ................................................................ 180
Summary of Message Bus Registers—0x05 ................................................................ 228
Summary of Message Bus Registers—0x31 ................................................................ 229
Memory Signals...................................................................................................... 233
Supported DDR3 DRAM Devices................................................................................ 235
Supported DDR3 Memory Configurations ................................................................... 235
Summary of Message Bus Registers—0x01 ................................................................ 236
PCI Express* 2.0 Signals ......................................................................................... 261
Possible Interrupts Generated From Events/Packets .................................................... 262
Summary of PCI Configuration Registers—0/23/0 ....................................................... 264
10/100 Ethernet Interface Signals ............................................................................ 309
Summary of PCI Configuration Registers—0/20/6 ....................................................... 311
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 327
Transmit Descriptor Word 0 (TDES0)......................................................................... 423
Transmit Descriptor Word 1 (TDES1)......................................................................... 426
Transmit Descriptor 2 (TDES2) ................................................................................. 426
Transmit Descriptor 3 (TDES3) ................................................................................. 426
Transmit Descriptor 6 (TDES6) ................................................................................. 426
Transmit Descriptor 7 (TDES7) ................................................................................. 427
Receive Descriptor Fields (RDES0) ............................................................................ 428
Receive Descriptor Fields 1 (RDES1) ......................................................................... 429
Receive Descriptor Fields 2 (RDES2) ......................................................................... 430
Receive Descriptor Fields 3 (RDES3) ......................................................................... 430
Receive Descriptor Fields 4 (RDES4) ......................................................................... 431
Receive Descriptor Fields 6 (RDES6) ......................................................................... 433
Receive Descriptor Fields 7 (RDES7) ......................................................................... 433
Signals.................................................................................................................. 435
Summary of PCI Configuration Registers—0/20/2 ....................................................... 437
Summary of PCI Configuration Registers—0/20/3 ....................................................... 453
Summary of PCI Configuration Registers—0/20/4 ....................................................... 471
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 486
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 549
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 569
SDIO/SD/eMMC Interface Signals ............................................................................. 591
SDIO/SD/eMMC Features......................................................................................... 592
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Contents—Intel® Quark™ SoC X1000
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
Summary of PCI Configuration Registers—0/20/0 ....................................................... 596
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 612
UART 0 Interface Signals......................................................................................... 663
UART 1 Interface Signals......................................................................................... 663
Baud Rates Achievable with Different DLAB Settings ................................................... 664
Summary of PCI Configuration Registers—0/20/1 ....................................................... 669
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 684
Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 694
I2C* Signals .......................................................................................................... 731
I2C* Definition of Bits in First Byte ........................................................................... 734
GPIO Signals ......................................................................................................... 738
Summary of PCI Configuration Registers—0/21/2 ....................................................... 739
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 755
Summary of Memory Mapped I/O Registers—BAR1 ..................................................... 777
SPI Interface Signals .............................................................................................. 787
SPI Clock Frequency Settings .................................................................................. 790
Summary of PCI Configuration Registers—0/21/0 ....................................................... 792
Summary of Memory Mapped I/O Registers—BAR0 ..................................................... 807
Miscellaneous Legacy Signals................................................................................... 816
Summary of PCI Configuration Registers—0/31/0 ....................................................... 817
Summary of Memory Mapped I/O Registers—RCBA..................................................... 827
Summary of I/O Registers....................................................................................... 832
Summary of I/O Registers—GPE0BLK ....................................................................... 835
Summary of I/O Registers—PM1BLK ......................................................................... 841
Legacy GPIO Signals............................................................................................... 845
Summary of I/O Registers—GBA .............................................................................. 846
Legacy SPI Signals ................................................................................................. 856
Summary of Memory Mapped I/O Registers—RCBA..................................................... 858
Counter Operating Modes........................................................................................ 874
Register Aliases ..................................................................................................... 876
8254 Interrupt Mapping .......................................................................................... 882
Summary of Memory Mapped I/O Registers—0xFED00000........................................... 883
RTC Signals........................................................................................................... 893
I/O Registers Alias Locations ................................................................................... 895
Indexed Registers .................................................................................................. 895
IRQAGENT Description ............................................................................................ 899
Interrupt Controller Connections .............................................................................. 900
Interrupt Status Registers ....................................................................................... 901
Content of Interrupt Vector Byte .............................................................................. 901
8259 I/O Registers Alias Locations ........................................................................... 907
Summary of I/O Registers....................................................................................... 907
I/O APIC Memory Mapped Registers ......................................................................... 921
Index Registers ..................................................................................................... 922
Summary of I/O Registers—WDTBA.......................................................................... 927
Debug Port and JTAG/TAP Signals ............................................................................ 935
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Intel® Quark™ SoC X1000—Revision History
Revision History
Date
Revision
August 2015
005
•
•
Updated Section 18.3.1, “DMA Mode Operation” on page 665
Updated Section 18.3.4, “Autoflow Control” on page 667
November 2014
004
•
•
Updated Section 9.2.3, “AC Power Applied: G3 to S4/S5 State Transition” on page 115
Updated Section 9.2.4, “Using PWR_BTN_B: Transition from S4/S5 to S0” on page 116
003
•
•
•
•
•
•
•
•
Updated
Updated
Updated
Updated
Updated
Updated
Updated
Updated
August 2014
Description
Table 23, “Hardware Straps” on page 57
subsection numbering under Section 12.6.2, “SPI DMA Block” on page 140
Table 27, “Power Supply Rail Ranges” on page 70
Table 28, “Maximum Supply Current: ICC Max” on page 71
Table 33, “RTC DC Characteristics” on page 74
Table 36, “USB 2.0 Differential Signal DC Characteristics” on page 77
Table 66, “RTC Power Well Timing Parameters” on page 115
Table 110, “SDIO/SD/eMMC Features” on page 592
May 2014
002
Updated Chapter 3 Ballout and Package Information
Updated Table 18 Power Management Interface Signals
Updated Table 23 Hardware Straps
Added Table 30, “Configurable IO (CFIO) Bi-directional Signal Groupings” on page 72 and Table 31,
“CFIO DC Characteristics” on page 73
Replaced Figure 19, “SoC Platform Clocking” on page 102
Removed ECC Scrubbing (Sections 12.7.3.1 - 12.7.3.10, Section 12.3.1)
Removed SPI DMA (Updated Section 12.3, Removed Sections 12.6.2.1 - 12.6.2.3, Added Register
Option Register 1(P_CFG_72) —Offset 72h)
Updated Table 49
Added Table 54 Message Types to Section 6.4 Message Bus Space
Updated Table 67
Added 12.7.9.2 Miscellaneous Legacy Signal Enables (HLEGACY)—Offset 0Ah
Updated Section 13.4.1 DRAM Rank Population (DRP)—Offset 0h
Added Table 78 Message Opcode Definition (Section 13.5)
Added Section 15.7, “MAC Descriptor Details”
Other changes are marked with change bars
October 2013
001
Initial Public Release
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Introduction—Intel® Quark™ SoC X1000
1.0
Introduction
1.1
About This Manual
This document is intended for Original Equipment Manufacturers and BIOS vendors
creating products based on the Intel® Quark™ SoC X1000 application processor.
Note:
Throughout this document, SoC is used as a general term and refers to all Intel®
Quark™ SoC X1000 SKUs, unless specifically noted otherwise.
This manual assumes a working knowledge of the vocabulary and principles of
interfaces and architectures such as PCI Express*, USB, SDIO/MMC, and ACPI.
Although some details of these features are described within this manual, refer to the
individual industry specifications listed in Table 1 for the complete details.
All PCI buses, devices and functions in this manual are abbreviated using the following
nomenclature; Bus:Device:Function. This manual abbreviates buses as Bn, devices as
Dn and functions as Fn. For example, Device 31 Function 0 is abbreviated as D31:F0,
Bus 1 Device 8 Function 0 is abbreviated as B1:D8:F0. Generally, the bus number is not
used, and can be considered to be Bus 0.
Table 1.
Industry Specifications
Specification
1.2
Location
PCI Express* Base Specification, Revision 2.0
http://www.pcisig.com/specifications
PCI Local Bus Specification, Revision 2.3 (PCI)
http://www.pcisig.com/specifications
PCI Power Management Specification, Revision 1.2
http://www.pcisig.com/specifications
Universal Serial Bus Specification (USB), Revision 2.0
http://www.usb.org/developers/docs
Advanced Configuration and Power Interface, Version 3.0 (ACPI)
http://www.acpi.info/spec.htm
Enhanced Host Controller Interface Specification for Universal
Serial Bus, Revision 1.0 (EHCI)
http://developer.intel.com/technology/usb/
ehcispec.htm
IEEE 802.3 Fast Ethernet
http://standards.ieee.org/getieee802/
AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6)
http://T13.org (T13 1410D)
IA-PC HPET (High Precision Event Timers) Specification,
Revision 1.0a
http://www.intel.com/content/www/us/en/
software-developers/software-developershpet-spec-1-0a.html
Component Overview
The Intel® Quark™ SoC X1000 processor is the next generation secure, low-power
Intel® Architecture (IA) SoC for deeply embedded applications. The SoC integrates the
Inte® QuarkTM SoC X1000 Core plus all the required hardware components to run offthe-shelf operating systems and to leverage the vast x86 software ecosystem.
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Intel® Quark™ SoC X1000—Introduction
To enable secure applications, the SoC secure SKUs feature an on-die Boot ROM that is
used to establish a hardware Root of Trust (RoT). The immutable code located within
the Boot ROM is used to initiate an iterative firmware authentication process ensuring
only trusted code is executed when taking the platform out of reset.
To facilitate low-cost platforms with sensitive Bill of Material (BOM) requirements, all
SoC clocks can be generated from a single crystal oscillator while all the required SoC
voltage levels can be derived from a single commercial off-the-shelf (COTS) voltage
regulator. In addition, the SoC provides an ECC-protected DRAM solution using only
standard x8 DDR3 devices.
The SoC also features a 512 Kbyte on-die embedded SRAM (eSRAM) that can be
configured to overlay regions of DRAM to provide low latency access to critical portions
of system memory. For robustness, the contents of this on-die eSRAM are also ECC
protected.
Figure 1.
Block Diagram
CPU Core
Clock
eSRAM
Host Bridge
JTAG
DDR3
Memory
Controller
AMBA Fabric
I/O
I/O
I/O
SPI
I/O
I/O
APIC
I/O
ROM
8259
I/O
HPET
8254
I/O
I/O
RTC
I/O
I/O
SDIO
I/O
GPIO
UART
I/O
I/O
USB 2.0
I/O
PMC
10/100 ETH
I/O
I/O
SPI
PCIe*
I2C*/GPIO
I/O
1.2.1
Legacy Bridge
SoC CPU Core Features
• 400 MHz maximum operating frequency
• Low power options to run at half or at quarter of maximum CPU frequency
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Introduction—Intel® Quark™ SoC X1000
• 32-bit address bus, 32-bit data bus
• 16 Kbyte shared instruction and data L1 cache.
1.2.2
System Memory Controller Features
• Single channel DDR3 memory controller with ECC support
• 16-bit data bus
• Supports up to two ranks total
• Supports DDR3 with 800 MT/s data rates
• x8 DRAM device data width
• 1 Gbit, 2 Gbit, and 4 Gbit DRAM device densities
• Total memory size from 128 Mbyte to 2 Gbyte
• Supports different physical mappings of bank addresses to optimize performance
• Out-of-order request processing to increase performance
• Aggressive power management to reduce power consumption
• Proactive page closing policies to close unused pages
• Supports soldered down DRAM devices
1.2.3
Embedded SRAM Features
• Low Latency 512 Kbyte on-die embedded SRAM
• Configurable to either overlay a 512 Kbyte block or overlay individual 4 Kbyte
pages of system memory
• ECC protected
1.2.4
Power Management Features
• Supports ACPI 3.0 specification
• Supports C0, C1, and C2 processor power states
• Supports S0, S3, and S4/S5 system power states
1.2.5
Security Features
• On-die Boot ROM provides Hardware Root of Trust (RoT) for firmware
authentication
1.2.6
PCI Express* Features
The SoC has two PCI Express* root ports, each supporting the PCI Express Base
specification Rev 2.0 at a maximum of 2.5 GT/s data transfer rates. Each root port is
configured as a x1 link.
• 128 Byte max payload size with the capability of splitting the request at 64 Byte
granularity
• Software-Initiated Link Power Management (D1, D2, D3Hot, and L1 States)
• PME event generation
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Intel® Quark™ SoC X1000—Introduction
1.2.7
Ethernet Features
• 10 and 100 Mbps data transfer rates with RMII interface to communicate with an
external Fast Ethernet PHY
• Full-duplex operation:
— IEEE 802.3x flow control support
— Optional forwarding of received pause control frames to the user application
• Half-duplex operation:
— CSMA/CD Protocol support
• Flexible address filtering modes:
— 64-bit Hash filter for multicast and unicast (DA) addresses
— Option to pass all multicast addressed frames
— Promiscuous mode to pass all frames without any filtering for network
monitoring
— Pass all incoming packets (as per filter) with a status report
• Programmable frame length to support Standard Ethernet frames with size up to
1522 bytes
• Enhanced Receive module for checking IPv4 header checksum and TCP, UDP, or
ICMP checksum encapsulated in IPv4 or IPv6 datagrams (Type 2)
• Support Ethernet frame time stamping as described in IEEE 1588-2002 and IEEE
1588-2008. The 64-bit timestamps are given in the transmit or receive status of
each frame.
1.2.8
USB2 Host Controller Features
• 2 host ports that support high-speed (480 Mbps), full-speed (12 Mbps), and lowspeed (1.5 Mbps) operation
• EHCI and OHCI host controllers
1.2.9
USB2 Device Controller Features
• Single device port that supports high-speed (480 Mbps) and full-speed (12 Mbps)
operation
1.2.10
SD/SDIO/eMMC Controller Features
• Host Controller provides a single port configurable as an SD, SDIO, or eMMC
interface
• SD Clock Frequency up to 50 MHz
• Supports SD Host Controller Standard Specification 3.0
• Supports SDIO card specification 3.0
• Supports SD Memory Card Specification 3.0
• Supports SD Memory Card Security Specification 1.01
• Supports eMMC Specification 4.41
1.2.11
I2C* Master Controller
• Two-wire I2C serial bus interface
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Introduction—Intel® Quark™ SoC X1000
• Two I2C speeds supported: Standard (100 Kbit/s) and Fast (400 Kbit/s) data rates
• Fully asynchronous I2C clock signal
• Master I2C operation
1.2.12
GPIO Features
• 16 GPIO pins provided
• 6 GPIO pins remain active during S3 and can be used to wake the system from the
Suspend state.
• Remaining 10 GPIO pins are powered during S0 state only and are not available in
S3
1.2.13
SPI Master Controller
• Two SPI Master controllers
• One Chip Select per master controller
• Configurable SCLK frequency from 1 kHz up to 25 MHz
1.2.14
High Speed UART Controller with DMA
• Two 16550 compliant UART controllers
• Supported Baud rates from 300 to 2764800
• Integrated DMA capability with hardware flow control
1.2.15
Legacy Bridge
The Legacy Bridge is a collection of hardware blocks critical to implement an Intel
Architecture compatible platform. Some of its key features are:
• A 20 MHz Serial Peripheral Interface (SPI) for Flash only - stores boot FW and
system configuration data
• A Power Management Controller (PMC) that controls many of the power
management features present in the SoC
• Legacy Bridge Components - Provides hardware blocks required to support legacy
PC platform features. The legacy bridge components include the RTC, Interrupt
Controllers, Timers and General Purpose I/Os (GPIO).
1.2.16
Package
The SoC is packaged in a Flip-Chip Ball Grid Array (FCBGA) package with 393 solder
balls with 0.593 mm ball pitch. The package dimensions are 15mm x 15mm.
1.3
Component Identification
The Intel® Quark™ SoC X1000 stepping is identified by both:
• Processor Family/Model/Stepping returned by the CPUID instruction. This always
returns 0x590 for SoC.
• Revision ID register of the Host Bridge, located at D0:F0. Reads of the register
reflect the stepping.
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Intel® Quark™ SoC X1000—Introduction
Table 2.
Component Identification
Vendor ID1
Device ID2
Revision ID3
Stepping
8086h
0958h
00h
A0h
Notes:
1.
The Vendor ID corresponds to bits 15-0 of the Vendor ID Register located at offset 00-01h in the PCI
configuration space of the device.
2.
The Device ID corresponds to bits 15-0 of the Device ID Register located at offset 02-03h in the PCI
configuration space of the device.
3.
The Revision ID corresponds to bits 7-0 of the Revision ID Register located at offset 08h in the PCI
configuration space of the device.
The SoC incorporates a variety of PCI functions as listed in Table 3. All devices reside
on PCI Bus 0 as shown in Figure 2.
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Introduction—Intel® Quark™ SoC X1000
Figure 2.
Intel® Quark™ SoC X1000 PCI View
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
PCI
ECAM
(Mem)
I2C*/GPIO F:2
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
RP0 F:1
PMC
Legacy Bridge
D:31,F:0
SDIO/eMMC F:0
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
GPIO
RTC
8254
8259
HPET
IO APIC
SPI
MAC0 F:6
MAC1 F:7
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Intel® Quark™ SoC X1000—Introduction
Table 3.
Intel® Quark™ SoC X1000 Device ID
Device Function
Description
Device ID
A0 SRID
D0:F0
Host Bridge
0958h
00h
D31:F0
Legacy Bridge
095Eh
00h
D23:F0
PCIe* Root Port 0
11C3h
00h
D23:F1
PCIe* Root Port 1
11C4h
00h
D20:F0
SDIO / eMMC Controller
08A7h
10h
D20:F1
HS-UART 0
0936h
10h
D20:F2
USB 2.0 Device
0939h
10h
D20:F3
USB EHCI Host Controller
0939h
10h
D20:F4
USB OHCI Host Controller
093Ah
10h
D20:F5
HS-UART 1
0936h
10h
D20:F6
10/100 Ethernet MAC 0
0937h
10h
D20:F7
10/100 Ethernet MAC 1
0937h
10h
D21:F0
SPI Controller 0
0935h
10h
D21:F1
SPI Controller 1
0935h
10h
I C* Controller and GPIO Controller
0934h
10h
D21:F2
2
§§
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Physical Interfaces—Intel® Quark™ SoC X1000
2.0
Physical Interfaces
Many interfaces contain physical pins. These groups of pins make up the physical
interfaces. This chapter summarizes the physical interfaces.
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Intel® Quark™ SoC X1000—Physical Interfaces
Figure 3.
Signals In Default System Pin List
DDR3_DQ[15:0]
DDR3_DQS[1:0]
DDR3_DQSB[1:0]
DDR3_DM[1:0]
DDR3_MA[15:0]
DDR3_BS[2:0]
DDR3_RASB
DDR3_CASB
DDR3_WEB
DDR3_CSB[1:0]
DDR3_ODT[1:0]
DDR3_CKE[1:0]
DDR3_CK[1:0]
DDR3_CKB[1:0]
DDR3_VREF
DDR3_ODTPU/DQPU/CMDPU
DDR3_IDRAM_PWROK
DDR3_ISYSPWRGOOD
DDR3_DRAMRSTB
MAC[0/1]_TXEN
MAC[0/1]_TXDATA[1:0]
MAC[0/1]_RXDV
MAC[0/1]_RXDATA[1:0]
MAC[0/1]_MDC
MAC[0/1]_MDIO
RMII_REF_CLK
PCIE_PETP[1:0]
PCIE_PETN[1:0]
PCIE_PERP[1:0]
PCIE_PERN[1:0]
PCIE_REFCLKN
PCIE_REFCLKP
PCIE_IRCOMP
PCIE_RBIAS
SD_DATA[7:0]
SD_CMD
SD_CLK
SD_WP
SD_CD_B
SD_LED
SD_PWR
USBD_DP
USBD_DN
USBH[1:0]_DP
USBH[1:0]_DN
USBH[1:0]_OC_B
IUSBCOMP
OUSBCOMP
USBH[1:0]_PWR_EN
CPU
Core
DDR3
Interface
IVCCRTCEXT
Legacy
Components
RTCX1
RTCX2
RTCRST_B
THERM_B
SMI_B
LSPI_SS_B
LSPI_SCK
Legacy Bridge
LSPI_MISO
Ethernet
RMII
Interface
LSPI_MOSI
RESET_BTN_B
PWR_BTN_B
WAKE_B
GPE_B
PCI Express* 2.0
Interface
S5_PG
Power
Management
Controller
Interface
S3_3V3_EN
S3_1V5_EN
S3_PG
S0_3V3_EN
S0_1V5_EN
S0_1V0_EN
S0_1P0_PG
SD/MMC
Interface
S0_PG
ODRAM_PWROK
OSYSPWRGOOD
SIU0_DCD_B
SIU0_DSR_B
Universal Serial
Bus 2.0
Interface
SIU0_DTR_B
HSUART
Interface
SIU0_RI_B
SIU[0/1]_CTS_B
SIU[0/1]_RTS_B
SIU[0/1]_RXD
SIU[0/1]_TXD
FLEX_CLK[2:0]
CKSYS25OUT
RMII_REF_CLK_OUT
REF[0/1]_OUTCLK_P
REF[0/1]_OUTCLK_N
OSC_COMP
XTAL_IN
XTAL_OUT
Internal Clocking
SPI
Interface
RTC_EXT_CLK_EN
PRDY_B
PREQ_B
TCK
TDI
TDO
TMS
TRST_B
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JTAG Port
SPI[0/1]_SS_B
SPI[0/1]_SCK
SPI[0/1]_MISO
SPI[0/1]_MOSI
I2C*
Interface
I2C_CLK
I2C_DATA
GPIO
Interface
GPIO_SUS[5:0]
GPIO[9:0]
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Physical Interfaces—Intel® Quark™ SoC X1000
2.1
Pin States Through Reset
This chapter describes the each signal state before, during, and directly after reset.
Additionally, some signals have internal pull-up/pull-down termination resistors, and
their values are also provided.
Table 4.
I/O Power Well Definitions
Power Type
Table 5.
Power Well Description
CORE
Core I/O, and everything else uses the CORE power well.
SUS
Devices outside of memory that must remain on in the S3 state use the SUS power well.
RTC
Devices that must be on in the S4/S5 state use the RTC power well.
Buffer Type Definitions
Buffer Type
Buffer Description
PCIe*
Table 6.
PCIe*, differential buffer type
SSTL-15
DDR3, 1.5V tolerant SSTL buffer type
DDI
DDR (TMDS, DP) 1.0V tolerant differential buffer type
CMOS[Voltage]
CMOS buffer type. [Voltage] can be of the following types: 1.05, 1.5, 1.8, and 3.3.
CMOS[Voltage]_OD
Open drain CMOS buffer type [Voltage] can be of the following types: 1.05, 1.5, 1.8 and
3.3.
Analog
Analog pins that do not have specific digital requirements. Often used for circuit
calibration or monitoring.
Default Buffer State Definitions
Buffer State
2.2
Description
High-Z
The SoC places this output in a high-impedance state. For inputs, external drivers are not
expected.
Do Not Care
The state of the input (driven or tristated) does not affect the SoC. For outputs, it is
assumed that the output buffer is in a high-impedance state.
VOH
The SoC drives this signal high.
VOL
The SoC drives this signal low.
Unknown
The SoC drives or expects an indeterminate value.
VIH
The SoC expects/requires the signal to be driven high.
VIL
The SoC expects/requires the signal to be driven low.
Pull-up
This signal is pulled high by a pull-up resistor (internal or external — internal value
specified in “Term” column).
Pull-down
This signal is pulled low by a pull-down resistor (internal or external — internal value
specified in “Term” column).
Running
The clock is toggling, or the signal is transitioning.
Off
The power plane for this signal is powered down. The SoC does not drive outputs, and
inputs should not be driven to the SoC. (VSS on output)
System Memory Signals
See Section 6.0 for more details of the DDR3 interface signals. Termination not listed.
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Intel® Quark™ SoC X1000—Physical Interfaces
Table 7.
System Memory Signals
Default Buffer State
Signal Name
DDR3_BS[2:0]
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CASB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_RASB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_WEB
O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_MA[15:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CK[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CKB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_CKE[1:0]
I/O
-
1.5V
SSTL-15
Off
VOL
VOL
VOL
DDR3_CSB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
VOH
DDR3_ODT[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
VOL
DDR3_DQ[15:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DM[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DQS[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_DQSB[1:0]
I/O
-
1.5V
SSTL-15
Off
High-Z
High-Z
High-Z
DDR3_IDRAM_PWROK
I
Ext
1.5V
CMOS-15
VIL
VIH
Pull-up
VIH
DDR3_ISYSPWRGOOD
I
Ext
1.5V
CMOS-15
VIL
VIL
Pull-up
VIH
DDR3_DRAMRSTB
Off
VOH
VOL
VOL/VOH(S3
Exit)
Reference
Off
Reference
Reference
Reference
Analog
Off
Analog
Analog
Analog
O
-
1.5V
CMOS-15
DDR3_VREF
I/O
-
1.5V
DDR3_ODTPU
I/O
-
1.5V
DDR3_DQPU
I/O
-
1.5V
Analog
Off
Analog
Analog
Analog
DDR3_CMDPU
I/O
-
1.5V
Analog
Off
Analog
Analog
Analog
2.3
PCI Express* 2.0 Signals
See “PCI Express* 2.0” on page 261 for more details of the interface signals.
Table 8.
PCI Express* 2.0 Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
PCIE_REFCLKP
I
-
1.05V
PCIe
Off
Off
Running/
Unknown
PCIE_REFCLKN
I
-
1.05V
PCIe
Off
Off
Running/
Unknown
PCIE_PETP[1:0]
O
-
1.05V
PCIe
Off
Off
PCIE_PETN[1:0]
O
-
1.05V
PCIe
Off
Off
VOL
VOL
PCIE_PERP[1:0]
I
-
1.05V
PCIe
Off
Off
High-Z
High-Z
PCIE_PERN[1:0]
PCIE_IRCOMP
PCIE_RBIAS
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VOL
Enter S0
Running/
Unknown
Running/
Unknown
VOL
I
-
1.05V
PCIe
Off
Off
High-Z
High-Z
I/O
-
1.5V
Analog
Off
Off
Analog
Analog
I
-
1.5V
Analog
Off
Off
Analog
Analog
November 2014
Document Number: 329676-004US
Physical Interfaces—Intel® Quark™ SoC X1000
2.4
Ethernet Interface Signals
See Chapter 15.0, “10/100 Mbps Ethernet” for more details of the Ethernet interface
signals.
Table 9.
Ethernet Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
RMII_REF_CLK
I
-
3.3V
CMOS3.3
Off
Off
Running/
Unknown
Running
MAC0_TXEN
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC0_TXDATA[1:0]
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC0_RXDV
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
MAC0_RXDATA[1:0]
I
-
3.3V
CMOS3.3
Off
Off
Unknown
Unknown
MAC0_MDC
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
MAC0_MDIO
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
MAC1_TXEN
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC1_TXDATA[1:0]
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
MAC1_RXDV
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
MAC1_RXDATA[1:0]
I
-
3.3V
CMOS3.3
Off
Off
Unknown
Unknown
MAC1_MDC
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
MAC1_MDIO
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
2.5
USB 2.0 Interface Signals
See Chapter 16.0, “USB 2.0” for more details of the USB 2.0 interface signals.
Table 10.
USB 2.0 Interface Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
USBH0_OC_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
USBH1_OC_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
USBH0_PWR_EN
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
USBH1_PWR_EN
O
Ext
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
USBH0_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH0_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH1_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBH1_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBD_DP
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
USBD_DN
I/O
-
3.3V
USB
Off
Off
High-Z
High-Z
I
-
1.05V
USB
Off
Off
Running/
Unknown
Running/
Unknown
USB_CLK96P
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Intel® Quark™ SoC X1000—Physical Interfaces
Table 10.
USB 2.0 Interface Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
USB_CLK96N
I
-
1.05V
USB
Off
Off
Running/
Unknown
Running/
Unknown
OUSBCOMP_P18
O
-
1.8V
Analog
Off
Off
Analog
Analog
IUSBCOMP_N18
I
-
1.8V
Analog
Off
Off
Analog
Analog
2.6
Integrated Clock Interface Signals
See Chapter 7.0, “Clocking” for more details of the Integrated Clock interface signals.
Table 11.
Integrated Clock Interface Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
XTAL_IN
I
-
1.05V
Analog
Running
Running
Running
Running
XTAL_OUT
O
-
1.05V
Analog
Running
Running
Running
Running
CKSYS25OUT
O
-
3.3V
CMOS3.3
Running
Running
Running
Running
REF0_OUTCLK_P
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF0_OUTCLK_N
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF1_OUTCLK_P
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
REF1_OUTCLK_N
O
-
1.05V
CMOS1.05
VOL
VOL
VOL
Running
FLEX0_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
FLEX1_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
FLEX2_CLK
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
RMII_REF_CLK_OUT
O
-
3.3V
CMOS3.3
VOL
VOL
VOL
Running
OSC_COMP
I
-
1.5V
Analog
Analog
Analog
Analog
Analog
HPLL_REFCLK_P
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
HPLL_REFCLK_N
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
PAD_BYPASS_CLK
I
-
1.05V
CMOS1.05
Off
Off
Running/
Unknown
Running/
Unknown
2.7
SDIO/SD/MMC Signals
See Chapter 17.0, “SDIO/SD/eMMC” for more details of the interface signals, including
different options based on port configuration.
Table 12.
SD/SDIO/MMC Signals (Sheet 1 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
SD_DATA[7:0]
I/O
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_CMD
I/O
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_CLK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
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November 2014
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Physical Interfaces—Intel® Quark™ SoC X1000
Table 12.
SD/SDIO/MMC Signals (Sheet 2 of 2)
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I
20k(L)
3.3V
CMOS3.3
Off
Off
Pull-down
Pull-down
SD_CD_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SD_LED
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SD_PWR
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SD_WP
2.8
High Speed UART Interface Signals
The SoC features two separate High Speed UARTs. However, only UART0 provides the
Modem Control pins DCD, DSR, DTR and RI.
See Chapter 18.0, “High Speed UART” for more details of the HSUART interface signals.
Table 13.
High Speed UART Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
SIU0_CTS_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DCD_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DSR_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_DTR_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU0_RI_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_RTS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU0_RXD
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU0_TXD
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU1_CTS_B
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU1_RTS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SIU1_RXD
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SIU1_TXD
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
I2C* Interface Signals
2.9
See Chapter 19.0, “I2C* Controller/GPIO Controller” for more details of the I2C
Interface signals.
Table 14.
I2C* Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I2C_DATA
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
I2C_CLK
I/O
Ext
3.3V
CMOS3.3_OD
Off
Off
Pull-up
Pull-up
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Intel® Quark™ SoC X1000—Physical Interfaces
2.10
Legacy Serial Peripheral Interface (SPI) Signals
See Section 21.7 for more details of the SPI signals.
Table 15.
Legacy SPI Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
LSPI_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
LSPI_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
LSPI_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
LSPI_MOSI
2.11
Serial Peripheral Interface (SPI)
See Chapter 20.0, “SPI Interface” for more details of the SPI signals.
Table 16.
SPI Signals
Default Buffer State
Signal Name
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI0_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SPI0_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SPI0_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI1_MOSI
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI1_MISO
I
20k(H)
3.3V
CMOS3.3
Off
Off
Pull-up
Pull-up
SPI1_SS_B
O
-
3.3V
CMOS3.3
Off
Off
VOH
VOH
SPI1_SCK
O
-
3.3V
CMOS3.3
Off
Off
VOL
VOL
SPI0_MOSI
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Physical Interfaces—Intel® Quark™ SoC X1000
2.12
Real Time Clock (RTC) Interface Signals
See Section 21.10 for more details of the RTC interface signals.
Table 17.
Real Time Clock (RTC) Interface Signals
Default Buffer State
Signal Name
RTCX1
Dir
Term
Power
Type
S4/S5
S3
Reset
Enter S0
I/O
-
2,048 Bytes (RXFIFOSIZE): Reserved.
18
1b
RO
IP Checksum Offload (Type 2) in Rx (RXTYP2COE): Reserved.
17
1b
RO
IP Checksum Offload (Type 1) in Rx (RXTYP1COE): Reserved.
16
1b
RO
Checksum Offload in Tx (TXCOESEL): Reserved.
15
0b
RO
AV Feature (AVSEL): Reserved.
14
0b
RO
Energy Efficient Ethernet (EEESEL): Reserved.
13
1b
RO
IEEE 1588-2008 Advanced Timestamp (TSVER2SEL): Reserved.
12
1b
RO
Only IEEE 1588-2002 Timestamp (TSVER1SEL): Reserved.
11
1b
RO
RMON Module (MMCSEL): Reserved.
10
0b
RO
PMT Magic Packet (MGKSEL): Reserved.
9
0b
RO
PMT Remote Wakeup (RWKSEL): Reserved.
8
1b
RO
SMA (MDIO) Interface (SMASEL): Reserved.
7
0b
RO
L3L4FLTREN: Reserved.
6
0b
RO
PCS registers (PCSSEL): Reserved.
5
0b
RO
Multiple MAC Address Registers (ADDMACADRSEL): Reserved.
4
1b
RO
HASH Filter (HASHSEL): Reserved.
3
0b
RO
Expanded DA Hash Filter (EXTHASHEN): Reserved.
2
1b
RO
Half-Duplex support (HDSEL): Reserved.
1
0b
RO
1000 Mbps Support (GMIISEL): Reserved.
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
0
15.7
1b
RO
Field Name (ID): Description
10 and 100 Mbps Support (MIISEL): Reserved.
MAC Descriptor Details
This section provides bit-field definitions of the current transmit and receive descriptor
registers described in Section 15.6, specifically:
• Current Host Transmit Descriptor Register (Register 18) (DMA_REG_18)—Offset
1048h
• Current Host Receive Descriptor Register (Register 19) (DMA_REG_19)—Offset
104Chh
15.7.1
Descriptor Overview
The descriptor structure has 8 DWORDS (32-bytes). The features of the descriptor
structure are:
• The descriptor structure is implemented to support buffers of up to 8 KB (useful for
Jumbo frames).
• There is a re-assignment of control and status bits in TDES0, TDES1, RDES0
(Advanced timestamp or IPC full offload configuration), and RDES1.
• The transmit descriptor stores the timestamp in TDES6 and TDES7.
• This receive descriptor structure is also used for storing the extended status
(RDES4) and timestamp (RDES6 and RDES7).
• You can select one of the following options for descriptor structure:
— If timestamping is enabled in Register 448 (Timestamp Control Register) or
Checksum Offload is enabled in Register 0 (MAC Configuration Register), the
software needs to allocate 32-bytes (8 DWORDS) of memory for every
descriptor. For this, the software should set Bit 7 (Alternate Descriptor Size) of
Register 0 (Bus Mode Register).
— If timestamping or Checksum Offload is not enabled, the extended descriptors
(DES4 to DES7) are not required. Therefore, the software can use alternate
descriptors with the default size of 16 bytes.
15.7.2
Descriptor Endianness
The descriptor addresses must be aligned to the bus width (Word, DWord, or LWord for
32-bit bus). The data bus is configured for little-endian format.
The structure of the descriptor with respect to the data bus endianness is as follows:
• Data Bus Endianness: Little-endian
• Descriptor Endianness: Same-endian
• Data Bus: 32-bit data bus
15.7.3
Transmit Descriptor
The transmit descriptor structure is shown in Figure 29. The application software must
program the control bits TDES0[31:18] during descriptor initialization. When the DMA
updates the descriptor, it writes back all the control bits except the OWN bit (which it
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clears) and updates the status bits[7:0]. The contents of the transmitter descriptor
word 0 (TDES0) through word 3 (TDES3) are given in Table 89 through Table 91,
respectively.
The snapshot of the timestamp to be taken can be enabled for a given frame by setting
Bit 25 (TTSE) of TDES0. When the descriptor is closed (that is, when the OWN bit is
cleared), the timestamp is written into TDES6 and TDES7. This is indicated by the
status Bit 17 (TTSS) of TDES0 shown in Figure 29. The contents of TDES6 and TDES7
are mentioned in Table 93 and Table 94.
Figure 29.
Transmit Descriptor Fields
The DMA always reads or fetches four DWORDS of the descriptor from system memory
to obtain the buffer and control information as shown in Figure 30. When the AV
feature is enabled, TDES0 has additional control bits[6:3] for Channel 1 and Channel 2.
For Channel 0, Bits [6:3] are ignored. Bits [6:3] are described in Table 89.
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10/100 Mbps Ethernet—Intel® Quark™ SoC X1000
Figure 30.
Transmit Descriptor Fetch (Read)
Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 1 of 3)
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA. When this bit is reset, it
indicates that the descriptor is owned by the Host. The DMA clears this bit either when it completes
the frame transmission or when the buffers allocated in the descriptor are read completely. The
ownership bit of the frame’s first descriptor must be set after all subsequent descriptors belonging
to the same frame have been set. This avoids a possible race condition between fetching a
descriptor and the driver setting an ownership bit.
30
IC: Interrupt on Completion
When set, this bit sets the Transmit Interrupt (Register 5[0]) after the present frame has been
transmitted.
29
LS: Last Segment
When set, this bit indicates that the buffer contains the last segment of the frame. When this bit is
set, the TBS1 or TBS2 field in TDES1 should have a non-zero value.
28
FS: First Segment
When set, this bit indicates that the buffer contains the first segment of a frame.
27
DC: Disable CRC
When this bit is set, the MAC does not append a cyclic redundancy check (CRC) to the end of the
transmitted frame. This is valid only when the first segment (TDES0[28]) is set.
26
DP: Disable Pad
When set, the MAC does not automatically add padding to a frame shorter than 64 bytes. When this
bit is reset, the DMA automatically adds padding and CRC to a frame shorter than 64 bytes, and the
CRC field is added despite the state of the DC (TDES0[27]) bit. This is valid only when the first
segment (TDES0[28]) is set.
25
TTSE: Transmit Timestamp Enable
When set, this bit enables IEEE1588 hardware timestamping for the transmit frame referenced by
the descriptor. This field is valid only when the Enable IEEE1588 Timestamping option is selected
during core configuration and the First Segment control bit (TDES0[28]) is set.
24
CRCR: CRC Replacement Control
When set, the MAC replaces the last four bytes of the transmitted packet with recalculated CRC
bytes. The host should ensure that the CRC bytes are present in the frame being transferred from
the Transmit Buffer. This bit is valid when the Enable SA, VLAN, and CRC Insertion on TX option is
selected during core configuration and the First Segment control bit (TDES0[28]) is set.
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Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 2 of 3)
Bit
Description
23:22
CIC: Checksum Insertion Control
These bits control the checksum calculation and insertion. The following list describes the bit
encoding:
• 2’b00: Checksum Insertion Disabled.
• 2’b01: Only IP header checksum calculation and insertion are enabled.
• 2’b10: IP header checksum and payload checksum calculation and insertion are enabled, but
pseudo-header checksum is not calculated in hardware.
• 2’b11: IP Header checksum and payload checksum calculation and insertion are enabled, and
pseudo-header checksum is calculated in hardware.
This field is valid when the Enable Transmit Full TCP/IP Checksum (Type 2) option is selected during
core configuration and the First Segment control bit (TDES0[28]) is set.
21
TER: Transmit End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to
the base address of the list, creating a descriptor ring.
20
TCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When TDES0[20] is set, TBS2 (TDES1[28:16]) is a “don’t
care” value. TDES0[21] takes precedence over TDES0[20].
19:18
VLIC: VLAN Insertion Control When set, these bits request the MAC to perform VLAN tagging or
untagging before transmitting the frames. If the frame is modified for VLAN tags, the MAC
automatically recalculates and replaces the CRC bytes.
The following list describes the values of these bits:
• 2'b00: Do not add a VLAN tag.
• 2'b01: Remove the VLAN tag from the frames before transmission. This option should be used
only with the VLAN frames.
• 2'b10: Insert a VLAN tag with the tag value programmed in Register 353 (VLAN Tag Inclusion or
Replacement Register).
• 2'b11: Replace the VLAN tag in frames with the Tag value programmed in Register 353 (VLAN
Tag Inclusion or Replacement Register). This option should be used only with the VLAN frames.
These bits are valid when the Enable SA, VLAN, and CRC Insertion on TX option is selected during
core configuration and the First Segment control bit (TDES0[28]) is set.
17
TTSS: Transmit Timestamp Status
This field is used as a status bit to indicate that a timestamp was captured for the described transmit
frame. When this bit is set, TDES2 and TDES3 have a timestamp value captured for the transmit
frame. This field is only valid when the descriptor’s Last Segment control bit (TDES0[29]) is set.
16
IHE: IP Header Error
When set, this bit indicates that the MAC transmitter detected an error in the IP datagram header.
The transmitter checks the header length in the IPv4 packet against the number of header bytes
received from the application and indicates an error status if there is a mismatch. For IPv6 frames, a
header error is reported if the main header length is not 40 bytes. Furthermore, the Ethernet
Length/Type field value for an IPv4 or IPv6 frame must match the IP header version received with
the packet. For IPv4 frames, an error status is also indicated if the Header Length field has a value
less than 0x5.
15
ES: Error Summary
Indicates the logical OR of the following bits:
• TDES0[14]: Jabber Timeout
• TDES0[13]: Frame Flush
• TDES0[11]: Loss of Carrier
• TDES0[10]: No Carrier
• TDES0[9]: Late Collision
• TDES0[8]: Excessive Collision
• TDES0[2]: Excessive Deferral
• TDES0[1]: Underflow Error
• TDES0[16]: IP Header Error
• TDES0[12]: IP Payload Error
14
JT: Jabber Timeout
When set, this bit indicates the MAC transmitter has experienced a jabber time-out. This bit is only
set when Bit 22 (Jabber Disable) of Register 0 (MAC Configuration Register) is not set.
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Table 89.
Transmit Descriptor Word 0 (TDES0) (Sheet 3 of 3)
Bit
Description
13
FF: Frame Flushed
When set, this bit indicates that the DMA or MTL flushed the frame because of a software Flush
command given by the CPU.
12
IPE: IP Payload Error
When set, this bit indicates that MAC transmitter detected an error in the TCP, UDP, or ICMP IP
datagram payload.
The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual
number of TCP, UDP, or ICMP packet bytes received from the application and issues an error status
in case of a mismatch.
11
LC: Loss of Carrier
When set, this bit indicates that a loss of carrier occurred during frame transmission (that is, the
gmii_crs_i signal was inactive for one or more transmit clock periods during frame transmission).
This is valid only for the frames transmitted without collision when the MAC operates in the halfduplex mode.
10
NC: No Carrier
When set, this bit indicates that the Carrier Sense signal form the PHY was not asserted during
transmission.
9
LC: Late Collision
When set, this bit indicates that frame transmission is aborted because of a collision occurring after
the collision window (64 byte-times, including preamble, in MII mode and 512 byte-times, including
preamble and carrier extension, in GMII mode). This bit is not valid if the Underflow Error bit is set.
8
EC: Excessive Collision
When set, this bit indicates that the transmission was aborted after 16 successive collisions while
attempting to transmit the current frame. If Bit 9 (Disable Retry) bit in the Register 0 (MAC
Configuration Register) is set, this bit is set after the first collision, and the transmission of the
frame is aborted.
7
VF: VLAN Frame
When set, this bit indicates that the transmitted frame is a VLAN-type frame.
6:3
CC: Collision Count (Status field)
These status bits indicate the number of collisions that occurred before the frame was transmitted.
This count is not valid when the Excessive Collisions bit (TDES0[8]) is set. The core updates this
status field only in the half-duplex mode.
-orSLOTNUM: Slot Number Control Bits in AV Mode
These bits indicate the slot interval in which the data should be fetched from the corresponding
buffers addressed by TDES2 or TDES3.
When the transmit descriptor is fetched, the DMA compares the slot number value in this field with
the slot interval maintained in the core (Register 11xx). It fetches the data from the buffers only if
there is a match in values. These bits are valid only for AV channels (not Channel 0).
2
ED: Excessive Deferral
When set, this bit indicates that the transmission has ended because of excessive deferral of over
24,288 bit times (155,680 bits times in 1,000-Mbps mode or if Jumbo Frame is enabled) if Bit 4
(Deferral Check) bit in Register 0 (MAC Configuration Register) is set high.
1
UF: Underflow Error
When set, this bit indicates that the MAC aborted the frame because the data arrived late from the
Host memory. Underflow Error indicates that the DMA encountered an empty transmit buffer while
transmitting the frame. The transmission process enters the Suspended state and sets both
Transmit Underflow (Register 5[5]) and Transmit Interrupt (Register 5[0]).
0
DB: Deferred Bit
When set, this bit indicates that the MAC defers before transmission because of the presence of
carrier. This bit is valid only in the half-duplex mode.
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Table 90.
Transmit Descriptor Word 1 (TDES1)
Bit
Description
31:29
SAIC: SA Insertion Control
These bits request the MAC to add or replace the Source Address field in the Ethernet frame with
the value given in the MAC Address 0 register. If the Source Address field is modified in a frame, the
MAC automatically recalculates and replaces the CRC bytes.
The Bit 31 specifies the MAC Address Register (1 or 0) value that is used for Source Address
insertion or replacement. The following list describes the values of Bits[30:29]:
• 2'b00: Do not include the source address.
• 2'b01: Include or insert the source address. For reliable transmission, the application must
provide frames without source addresses.
• 2'b10: Replace the source address. For reliable transmission, the application must provide
frames with source addresses.
• 2'b11: Reserved
These bits are valid in the GMAC-DMA, GMAC-AXI, and GMAC-AHB configurations when the Enable
SA, VLAN, and CRC Insertion on TX is selected during core configuration and when the First
Segment control bit (TDES0[28]) is set.
28:16
TBS2: Transmit Buffer 2 Size
This field indicates the second data buffer size in bytes. This field is not valid if TDES0[20] is set.
15:13
12:0
Table 91.
Reserved
TBS1: Transmit Buffer 1 Size
These bits indicate the first data buffer byte size, in bytes. If this field is 0, the DMA ignores this
buffer and uses Buffer 2 or the next descriptor, depending on the value of TCH (TDES0[20]).
Transmit Descriptor 2 (TDES2)
Bit
31:0
Table 92.
Description
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There is no limitation on the buffer address
alignment.
Transmit Descriptor 3 (TDES3)
Bit
31:0
Table 93.
Description
Buffer 2 Address Pointer (Next Descriptor Address)
Indicates the physical address of Buffer 2 when a descriptor ring structure is used. If the Second
Address Chained (TDES1[24]) bit is set, this address contains the pointer to the physical memory
where the Next Descriptor is present. The buffer address pointer must be aligned to the bus width
only when TDES1[24] is set. (LSBs are ignored internally.)
Transmit Descriptor 6 (TDES6)
Bit
Description
31:0
TTSL: Transmit Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp captured for the
corresponding transmit frame. This field has the timestamp only if the Last Segment bit (LS) in the
descriptor is set and Timestamp status (TTSS) bit is set.
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Table 94.
Transmit Descriptor 7 (TDES7)
Bit
31:0
15.7.4
Description
TTSH: Transmit Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the
corresponding receive frame. This field has the timestamp only if the Last Segment bit (LS) in the
descriptor is set and Timestamp status (TTSS) bit is set.
Receive Descriptor
The structure of the received descriptor is shown in Figure 31. It has 32 bytes of
descriptor data (8 DWORDs).
Figure 31.
Receive Descriptor Fields
The contents of RDES0 are identified in Table 95. The contents of RDES1 through
RDES3 are identified in Table 96 through Table 98, respectively.
Note:
Some of the bit functions of RDES0 are not backward compatible to Release 3.41a and
previous versions. These bits are Bit 7, Bit 0, and Bit 5. The function of Bit 5 is
backward compatible to Release 3.30a and previous versions.
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Table 95.
Receive Descriptor Fields (RDES0) (Sheet 1 of 2)
Bit
Description
31
OWN: Own Bit
When set, this bit indicates that the descriptor is owned by the DMA of the DWC_gmac. When this
bit is reset, this bit indicates that the descriptor is owned by the Host. The DMA clears this bit either
when it completes the frame reception or when the buffers that are associated with this descriptor
are full.
30
AFM: Destination Address Filter Fail
When set, this bit indicates a frame that failed in the DA Filter in the MAC.
29:16
FL: Frame Length
These bits indicate the byte length of the received frame that was transferred to host memory
(including CRC). This field is valid when Last Descriptor (RDES0[8]) is set and either the Descriptor
Error (RDES0[14]) or Overflow Error bits are reset. The frame length also includes the two bytes
appended to the Ethernet frame when IP checksum calculation (Type 1) is enabled and the received
frame is not a MAC control frame.
This field is valid when Last Descriptor (RDES0[8]) is set. When the Last Descriptor and Error
Summary bits are not set, this field indicates the accumulated number of bytes that have been
transferred for the current frame.
15
ES: Error Summary
Indicates the logical OR of the following bits:
• RDES0[1]: CRC Error
• RDES0[3]: Receive Error
• RDES0[4]: Watchdog Timeout
• RDES0[6]: Late Collision
• RDES0[7]: Giant Frame
• RDES4[4:3]: IP Header or Payload Error
• RDES0[11]: Overflow Error
• RDES0[14]: Descriptor Error
This field is valid only when the Last Descriptor (RDES0[8]) is set.
14
DE: Descriptor Error
When set, this bit indicates a frame truncation caused by a frame that does not fit within the current
descriptor buffers, and that the DMA does not own the Next Descriptor. The frame is truncated. This
field is valid only when the Last Descriptor (RDES0[8]) is set.
13
SAF: Source Address Filter Fail
When set, this bit indicates that the SA field of frame failed the SA Filter in the MAC.
12
LE: Length Error
When set, this bit indicates that the actual length of the frame received and that the Length/ Type
field does not match. This bit is valid only when the Frame Type (RDES0[5]) bit is reset.
11
OE: Overflow Error
When set, this bit indicates that the received frame was damaged because of buffer overflow in MTL.
Note: This bit is set only when the DMA transfers a partial frame to the application. This happens
only when the Rx FIFO is operating in the threshold mode. In the store-and-forward mode, all
partial frames are dropped completely in Rx FIFO.
10
VLAN: VLAN Tag
When set, this bit indicates that the frame to which this descriptor is pointing is a VLAN frame
tagged by the MAC. The VLAN tagging depends on checking the VLAN fields of received frame based
on the VLAN Tag Register (Register 7) (GMAC_REG_7)—Offset 1Ch setting.
9
FS: First Descriptor
When set, this bit indicates that this descriptor contains the first buffer of the frame. If the size of
the first buffer is 0, the second buffer contains the beginning of the frame. If the size of the second
buffer is also 0, the next Descriptor contains the beginning of the frame.
8
LS: Last Descriptor
When set, this bit indicates that the buffers pointed to by this descriptor are the last buffers of the
frame.
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Table 95.
Table 96.
Receive Descriptor Fields (RDES0) (Sheet 2 of 2)
Bit
Description
7
Timestamp Available, IP Checksum Error (Type1), or Giant Frame
When Advanced Timestamp feature is present, when set, this bit indicates that a snapshot of the
Timestamp is written in descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last
Descriptor bit (RDES0[8]) is set.
When IP Checksum Engine (Type 1) is selected, this bit, when set, indicates that the 16-bit IPv4
Header checksum calculated by the core did not match the received checksum bytes.
Otherwise, this bit, when set, indicates the Giant Frame Status. Giant frames are larger than 1,518byte (or 1,522-byte for VLAN or 2,000-byte when Bit 27 (2KPE) of MAC Configuration register is
set) normal frames and larger than 9,018-byte (9,022-byte for VLAN) frame when Jumbo Frame
processing is enabled.
6
LC: Late Collision
When set, this bit indicates that a late collision has occurred while receiving the frame in the halfduplex mode.
5
FT: Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater
than or equal to 16’h0600). When this bit is reset, it indicates that the received frame is an
IEEE802.3 frame. This bit is not valid for Runt frames less than 14 bytes.
4
RWT: Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current
frame and the current frame is truncated after the Watchdog Timeout.
3
RE: Receive Error
When set, this bit indicates that the gmii_rxer_i signal is asserted while gmii_rxdv_i is asserted
during frame reception. This error also includes carrier extension error in the GMII and half-duplex
mode. Error can be of less or no extension, or error (rxd ≠ 0f) during extension.
2
DE: Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd
nibbles). This bit is valid only in the MII Mode.
1
CE: CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received
frame. This field is valid only when the Last Descriptor (RDES0[8]) is set.
0
Extended Status Available/Rx MAC Address
When either Advanced Timestamp or IP Checksum Offload (Type 2) is present, this bit, when set,
indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only when
the Last Descriptor bit (RDES0[8]) is set.
When Advance Timestamp Feature or IPC Full Offload is not selected, this bit indicates Rx MAC
Address status. When set, this bit indicates that the Rx MAC Address registers value (1 to 15)
matched the frame’s DA field. When reset, this bit indicates that the Rx MAC Address Register 0
value matched the DA field.
Receive Descriptor Fields 1 (RDES1) (Sheet 1 of 2)
Bit
Description
31
DIC: Disable Interrupt on Completion
When set, this bit prevents setting the Status Register’s RI bit (CSR5[6]) for the received frame
ending in the buffer indicated by this descriptor. This, in turn, disables the assertion of the interrupt
to Host because of RI for that frame.
30:29
Reserved
28:16
RBS2: Receive Buffer 2 Size
These bits indicate the second data buffer size, in bytes. The buffer size must be a multiple of 4, 8,
or 16, depending on the bus widths (32, 64, or 128, respectively), even if the value of RDES3
(buffer2 address pointer) is not aligned to bus width. If the buffer size is not an appropriate multiple
of 4, 8, or 16, the resulting behavior is undefined. This field is not valid if RDES1[14] is set.
15
RER: Receive End of Ring
When set, this bit indicates that the descriptor list reached its final descriptor. The DMA returns to
the base address of the list, creating a descriptor ring.
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Table 96.
Receive Descriptor Fields 1 (RDES1) (Sheet 2 of 2)
Bit
Description
14
RCH: Second Address Chained
When set, this bit indicates that the second address in the descriptor is the Next Descriptor address
rather than the second buffer address. When this bit is set, RBS2 (RDES1[28:16]) is a “don’t care”
value. RDES1[15] takes precedence over RDES1[14].
13
12:0
Table 97.
Table 98.
Reserved
RBS1: Receive Buffer 1 Size
Indicates the first data buffer size in bytes. The buffer size must be a multiple of 4, 8, or 16,
depending upon the bus widths (32, 64, or 128), even if the value of RDES2 (buffer1 address
pointer) is not aligned. When the buffer size is not a multiple of 4, 8, or 16, the resulting behavior is
undefined. If this field is 0, the DMA ignores this buffer and uses Buffer 2 or next descriptor
depending on the value of RCH (Bit 14).
Receive Descriptor Fields 2 (RDES2)
Bit
Description
31:0
Buffer 1 Address Pointer
These bits indicate the physical address of Buffer 1. There are no limitations on the buffer address
alignment except for the following condition: The DMA uses the configured value for its address
generation when the RDES2 value is used to store the start of frame. The DMA performs a write
operation with the RDES2[3:0, 2:0, or 1:0] bits as 0 during the transfer of the start of frame but the
frame data is shifted as per the actual Buffer address pointer. The DMA ignores RDES2[3:0, 2:0, or
1:0] (corresponding to bus width of 128, 64, or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
Receive Descriptor Fields 3 (RDES3)
Bit
Description
31:0
Buffer 2 Address Pointer (Next Descriptor Address)
These bits indicate the physical address of Buffer 2 when a descriptor ring structure is used. If the
Second Address Chained (RDES1[24]) bit is set, this address contains the pointer to the physical
memory where the Next Descriptor is present.
If RDES1[24] is set, the buffer (Next Descriptor) address pointer must be bus width-aligned
(RDES3[3, 2, or 1:0] = 0, corresponding to a bus width of 128, 64, or 32. LSBs are ignored
internally.) However, when RDES1[24] is reset, there are no limitations on the RDES3 value, except
for the following condition: The DMA uses the configured value for its buffer address generation
when the RDES3 value is used to store the start of frame. The DMA ignores RDES3 [3, 2, or 1:0]
(corresponding to a bus width of 128, 64, or 32) if the address pointer is to a buffer where the
middle or last part of the frame is stored.
The status written is as shown in Table 99. The status is written only when there is
status related to IPC or timestamp available. The availability of extended status is
indicated by Bit 0 of RDES0. This status is available only when the Advance Timestamp
or IPC Full Offload feature is selected.
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Table 99.
Receive Descriptor Fields 4 (RDES4) (Sheet 1 of 2)
Bit
Description
31:28
Reserved
27:26
Layer 3 and Layer 4 Filter Number Matched
These bits indicate the number of the Layer 3 and Layer 4 Filter that matched the received frame.
• 00: Filter 0
• 01: Filter 1
• 10: Filter 2
• 11: Filter 3
This field is valid only when Bit 24 or Bit 25 is set high. When more than one filter matches, these
bits give only the lowest filter number.
25
Layer 4 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 4 Port
Number fields. This status is given only when one of the following conditions is true:
• Layer 3 fields are not enabled and all enabled Layer 4 fields match.
• All enabled Layer 3 and Layer 4 filter fields match.
When more than one filter matches, this bit gives the layer 4 filter status of filter indicated by Bits
[27:26].
24
Layer 3 Filter Match
When set, this bit indicates that the received frame matches one of the enabled Layer 3 IP Address
fields.
This status is given only when one of the following conditions is true:
• All enabled Layer 3 fields match and all enabled Layer 4 fields are bypassed.
• All enabled filter fields match.
When more than one filter matches, this bit gives the layer 3 filter status of filter indicated by Bits
[27:26].
23:21
Reserved
20:18
VLAN Tag Priority Value
These bits give the VLAN tag’s user value in the received packet. These bits are valid only when the
RDES4 Bits 16 and 17 are set.
These bits are available only when you select the AV feature.
17
AV Tagged Packet Received
When set, this bit indicates that an AV tagged packet is received. Otherwise, this bit indicates that
an untagged AV packet is received. This bit is valid when Bit 16 is set.
This bit is available only when you select the AV feature.
16
AV Packet Received
When set, this bit indicates that an AV packet is received. This bit is available only when you select
the AV feature.
15
Reserved
14
Timestamp Dropped
When set, this bit indicates that the timestamp was captured for this frame but got dropped in the
MTL Rx FIFO because of overflow. This bit is available only when you select the Advanced
Timestamp feature. Otherwise, this bit is reserved.
13
PTP Version
When set, this bit indicates that the received PTP message is having the IEEE 1588 version 2
format. When reset, it has the version 1 format. This bit is available only when you select the
Advanced Timestamp feature. Otherwise, this bit is reserved.
12
PTP Frame Type
When set, this bit indicates that the PTP message is sent directly over Ethernet. When this bit is not
set and the message type is non-zero, it indicates that the PTP message is sent over UDP-IPv4 or
UDP-IPv6. The information about IPv4 or IPv6 can be obtained from Bits 6 and 7.
This bit is available only when you select the Advanced Timestamp feature.
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Table 99.
Receive Descriptor Fields 4 (RDES4) (Sheet 2 of 2)
Bit
11:8
Description
Message Type
These bits are encoded to give the type of the message received.
• 0000: No PTP message received
• 0001: SYNC (all clock types)
• 0010: Follow_Up (all clock types)
• 0011: Delay_Req (all clock types)
• 0100: Delay_Resp (all clock types)
• 0101: Pdelay_Req (in peer-to-peer transparent clock)
• 0110: Pdelay_Resp (in peer-to-peer transparent clock)
• 0111: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)
• 1000: Announce • 1001: Management
• 1010: Signaling • 1011-1110: Reserved
• 1111: PTP packet with Reserved message type
These bits are available only when you select the Advance Timestamp feature.
Note: Values 1000, 1001, and 1010 are not backward compatible with release 3.50a.
7
IPv6 Packet Received
When set, this bit indicates that the received packet is an IPv6 packet. This bit is updated only when
Bit 10 (IPC) of MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h) is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
6
IPv4 Packet Received
When set, this bit indicates that the received packet is an IPv4 packet. This bit is updated only when
Bit 10 (IPC) of MAC Configuration Register (Register 0) (GMAC_REG_0)—Offset 0h) is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
5
IP Checksum Bypassed
When set, this bit indicates that the checksum offload engine is bypassed. This bit is available when
you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
4
IP Payload Error
When set, this bit indicates that the 16-bit IP payload checksum (that is, the TCP, UDP, or ICMP
checksum) that the core calculated does not match the corresponding checksum field in the
received segment. It is also set when the TCP, UDP, or ICMP segment length does not match the
payload length value in the IP Header field. This bit is valid when either Bit 7 or Bit 6 is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
3
IP Header Error
When set, this bit indicates that either the 16-bit IPv4 header checksum calculated by the core does
not match the received checksum bytes, or the IP datagram version is not consistent with the
Ethernet Type value. This bit is valid when either Bit 7 or Bit 6 is set.
This bit is available when you select the Enable Receive Full TCP/IP Checksum (Type 2) feature.
2:0
IP Payload Type
These bits indicate the type of payload encapsulated in the IP datagram processed by the Receive
Checksum Offload Engine (COE). The COE also sets these bits to 2'b00 if it does not process the IP
datagram’s payload due to an IP header error or fragmented IP.
• 3'b000: Unknown or did not process IP payload
• 3'b001: UDP
• 3'b010: TCP
• 3'b011: ICMP
• 3’b1xx: Reserved
This bit is valid when either Bit 7 or Bit 6 is set. This bit is available when you select the Enable
Receive Full TCP/IP Checksum (Type 2) feature.
RDES6 and RDES7 contain the snapshot of the timestamp. The availability of the
snapshot of the timestamp in RDES6 and RDES7 is indicated by Bit 7 in the RDES0
descriptor. The contents of RDES6 and RDES7 are identified in Table 100 and Table 101,
respectively.
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Table 100.
Table 101.
Receive Descriptor Fields 6 (RDES6)
Bit
Description
31:0
RTSL: Receive Frame Timestamp Low
This field is updated by DMA with the least significant 32 bits of the timestamp captured for the
corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive
frame which is indicated by Last Descriptor status bit (RDES0[8]).
Receive Descriptor Fields 7 (RDES7)
Bit
Description
31:0
RTSH: Receive Frame Timestamp High
This field is updated by DMA with the most significant 32 bits of the timestamp captured for the
corresponding receive frame. This field is updated by DMA only for the last descriptor of the receive
frame which is indicated by Last Descriptor status bit (RDES0[8]).
§§
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Intel® Quark™ SoC X1000
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USB 2.0—Intel® Quark™ SoC X1000
16.0
USB 2.0
The Intel® Quark™ SoC X1000 USB subsystem provides a two-port USB 2.0 Host
Controller and one USB 2.0 Device port.
16.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 102.
Signals
Signal Name
USBH[0/1]_DP
USBH[0/1]_DN
Direction/
Type
I/O
Description
Universal Serial Bus Host Port 0 and Port 1. Differentials: Bus Data/
Address/Command Bus
USBH0_OC_B
USBH1_OC_B
I
Over current Indicators: These signals set corresponding bits in the USB
controller to indicate that an over current condition has occurred.
Overcurrent indicators are provided for both Host ports.
USBH0_PWR_EN
USBH1_PWR_EN
O
Power Enable signal to the USB host port
USBD_DP
USBD_DN
I/O
Universal Serial Bus Device Port. Differentials: Bus Data/ Address/
Command Bus
OUSBCOMP
O
RCOMP OUT. Note: Please check the Platform Design Guide for connection
details for this COMP pin.
IUSBCOMP
I
RCOMP IN. Note: Please check the Platform Design Guide for connection
details for this COMP pin.
16.2
Features
16.2.1
USB2.0 Host Controller Features
• 2-Port USB 2.0 Host Controller compatible with the following standards:
— Universal Serial Bus Specification (Revision 2.0, April 27, 2000)
— Enhanced Host Controller Interface Specification for Universal Serial Bus
(Revision1.0, March 12, 2002)
— EHCI 1.1 Addendum (Revision v0.6, October 2007)
— OpenHCI: Open Host Controller Interface Specification for USB (Release 1.0a,
September 14, 1999)
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• EHCI features
Supported:
— 512-byte Packet Buffer depth for in/out data buffering
— Programmable Packet Buffer depth
— Extended capability pointer (EECP = 8’hC0)
— Programmable frame list flag
— 32-bit only addressing capability
— Per port power control
— PCI Power Management
Not supported:
— Descriptor/data prefetching
— Asynchronous schedule park capability
— HSIC functionality
— Link Power Management (LPM) ECN
• OHCI features
Supported:
— One OHCI companion controller
— Per port power control
Not supported:
— Keyboard/Mouse legacy interface
16.2.2
USB2.0 Device Features
• High-speed (480 Mbps) and full-speed (12 Mbps) operation
• 3 logical endpoints in addition to logical endpoint 0
• 1 configuration in addition to configuration 0
• Enables user-configurable endpoint information
• Multiple data packets for each OUT endpoint (Multiple Receive FIFO).
• Both DMA option and Slave-Only modes
• True scatter-gather DMA implementation
• Descriptor-based memory structures in application memory when in DMA mode
16.3
References
• USB 2.0 specification at http://www.usb.org/developers/docs
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USB 2.0—Intel® Quark™ SoC X1000
16.4
Register Map
Figure 32.
USB Register Map
Memory Space
EHCI Host
PCI Header
D:20,F:3
PCI Space
CPU
Core
MBAR
Host Bridge
D:0,F:0
EHCI Host
Mem
Registers
PCI
CAM
(I/O)
Bus 0
PCIe*
D:23
SPI1 F:1
I2C*/GPIO F:2
IO Fabric
D:21
SPI0 F:0
Memory Space
OHCI Host
PCI Header
D:20,F:4
PCI
ECAM
(Mem)
RP0 F:0
MBAR
RP0 F:1
OHCI Host
Mem
Registers
Legacy Bridge
D:31, F:0
SDIO/eMMC F:0
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
Memory Space
USB Device
PCI Header
D:20,F:2
HSUART0 F:1
MBAR
MAC0 F:6
USB Device
Mem
Registers
MAC1 F:7
See Chapter 5.0, “Register Access Methods” for additional information.
16.5
PCI Configuration Registers
16.5.1
USB Device
Table 103.
Summary of PCI Configuration Registers—0/20/2
Offset Start
Offset End
Register ID—Description
Default
Value
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
0939h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
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Table 103.
Offset Start
Summary of PCI Configuration Registers—0/20/2 (Continued)
Offset End
Default
Value
Register ID—Description
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C03FE10h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 442
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 443
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 443
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 444
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 444
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 444
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 445
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 445
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 446
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 446
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 446
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 447
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 447
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 447
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 448
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 449
00h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 449
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 450
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 450
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 450
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 451
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 451
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 452
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 452
00000000h
86h
16.5.1.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:2] + 0h
Default: 8086h
15
12
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
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Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.1.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:2] + 2h
Default: 0939h
15
0
0
0
8
1
0
0
4
1
0
0
1
0
1
1
0
0
1
value
0
12
Bit
Range
Default &
Access
0939h
RO
15: 0
16.5.1.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:2] + 4h
Default: 0000h
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
8
RSVD
0
RSVD0
0
12
IntrDis
15
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
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Bit
Range
Default &
Access
0h
RO
0
16.5.1.4
Description
Reserved (RSVD): Reserved.
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:2] + 6h
Default: 0010h
Bit
Range
16.5.1.5
Default &
Access
0
1
0
0
0
0
RSVD1
0
IntrStatus
0
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
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Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:2] + 8h
Default: 0C03FE10h
0
0
1
1
0
0
20
0
0
0
16.5.1.6
0
0
1
1
12
1
1
1
subClassCode
0
16
1
8
1
1
1
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
24
classCode
0
28
progIntf
31
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
FEh
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:2] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.1.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:2] + Dh
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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16.5.1.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:2] + Eh
Default: 80h
7
4
0
0
0
multiFnDev
Bit
Range
16.5.1.9
0
0
0
0
cfgHdrFormat
1
0
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:2] + Fh
Default: 00h
4
Bit
Range
start_bist
0
0
0
RSVD
0
BIST_capable
0
0
Default &
Access
0
0
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
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16.5.1.10
Bit
Range
Default &
Access
3: 0
0h
RO
Description
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
16.5.1.11
0
0
0
0
RSVD
0
4
0
0
0
0
0
isIO
0
20
memType
0
24
address
0
28
prefetchable
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:2] + 28h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
28
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Bit
Range
Default &
Access
0h
RO
31: 0
16.5.1.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:2] + 2Ch
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.1.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:2] + 2Eh
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
15: 0
16.5.1.14
Default &
Access
0h
RO
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:2] + 30h
Default: 00000000h
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0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
16.5.1.15
0
0
0
0
0
0
0
0
AddrDecodeEn
0
24
ROM_base_addr
0
28
RSVD
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:2] + 34h
Default: 00000080h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
Bit
Range
16.5.1.16
0
0
0
0
0
0
value
RSVD0
0
28
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:2] + 3Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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16.5.1.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:2] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
7: 0
16.5.1.18
Default &
Access
Description
03h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:2] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:2] + 3Fh
Default: 00h
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Datasheet
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Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:2] + 80h
Default: 01h
7
4
0
0
0
0
0
0
1
value
0
0
16.5.1.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:2] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
value
1
0
16.5.1.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
August 2015
Document Number: 329676-005US
PMC: [B:0, D:20, F:2] + 82h
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Intel® Quark™ SoC X1000—USB 2.0
Default: 4803h
16.5.1.23
0
4
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
8
1
DSI
0
aux_curr
0
D1_support
12
1
PME_support
0
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:2] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
0
0
1
0
RSVD
0
4
0
0
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
15
14: 13
Intel® Quark™ SoC X1000
Datasheet
448
power_state
Description
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.1.24
Default &
Access
Description
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:2] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.1.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:2] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
Default &
Access
7: 0
0h
RO
August 2015
Document Number: 329676-005US
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Intel® Quark™ SoC X1000
Datasheet
449
Intel® Quark™ SoC X1000—USB 2.0
16.5.1.26
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:2] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
16.5.1.27
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:2] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.1.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability structure
in the chain
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:2] + A2h
Default: 0100h
Intel® Quark™ SoC X1000
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0
0
1
0
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
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Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.1.29
Default &
Access
Description
15: 9
0h
RO
RSVD0 (RSVD0): Reserved
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:2] + A4h
Default: 00000000h
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
address
0
24
Bit
Range
16.5.1.30
0
0
RSVD0
31
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:2] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
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Datasheet
451
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
16.5.1.31
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:2] + ACh
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
16.5.1.32
0
MSIMask
RSVD0
0
28
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:2] + B0h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
Intel® Quark™ SoC X1000
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452
0
4
value
RSVD0
0
28
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Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.2
USB EHCI
Table 104.
Summary of PCI Configuration Registers—0/20/3
Offset Start
Offset End
Default
Value
Register ID—Description
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
0939h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C032010h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 457
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 458
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 459
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 459
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 459
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 460
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 460
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 460
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 461
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 461
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 462
00h
60h
60h
“Serial Bus Release Number Register (SBRN)—Offset 60h” on page 462
20h
61h
61h
“Frame Length Adjustment Register (FLADJ)—Offset 61h” on page 462
20h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 463
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 463
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 463
F803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 464
0008h
86h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 465
00h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 465
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 465
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 466
C0h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 466
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 467
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 467
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 468
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 468
00000000h
C0h
C3h
“USB Legacy Support Extended Capability (USBLEGSUP)—Offset C0h” on
page 468
00000001h
C4h
C7h
“USB Legacy Support Control/Status (USBLEGCTLSTS)—Offset C4h” on page 469
00000000h
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Intel® Quark™ SoC X1000—USB 2.0
16.5.2.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:3] + 0h
Default: 8086h
15
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
1
0
0
1
value
1
12
Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.2.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:3] + 2h
Default: 0939h
15
12
0
0
0
8
1
0
0
4
1
0
0
1
1
0
value
0
Bit
Range
Default &
Access
0939h
RO
15: 0
16.5.2.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:3] + 4h
Default: 0000h
Bit
Range
Default &
Access
15: 11
0h
RO
Intel® Quark™ SoC X1000
Datasheet
454
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
8
RSVD
0
RSVD0
0
12
IntrDis
15
Description
RSVD0 (RSVD0): Reserved
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.4
Default &
Access
Description
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:3] + 6h
Default: 0010h
Bit
Range
Default &
Access
0
1
0
0
0
0
RSVD1
0
0
IntrStatus
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.5.2.5
Default &
Access
Description
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:3] + 8h
Default: 0C032010h
0
1
1
0
0
0
0
0
16.5.2.6
0
16
0
0
1
1
12
0
0
1
0
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
20
progIntf
0
24
classCode
0
28
subClassCode
31
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
20h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:3] + Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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USB 2.0—Intel® Quark™ SoC X1000
16.5.2.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:3] + Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:3] + Eh
Default: 80h
7
4
0
0
multiFnDev
Bit
Range
16.5.2.9
0
0
0
0
0
cfgHdrFormat
1
0
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:3] + Fh
Default: 00h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
457
Intel® Quark™ SoC X1000—USB 2.0
7
4
0
0
0
0
0
0
comp_code
RSVD
BIST_capable
Bit
Range
16.5.2.10
0
start_bist
0
0
Default &
Access
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
3: 0
0h
RO
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:3] + 10h
Default: 00000000h
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
4
0
RSVD
0
0
0
0
0
0
0
0
0
isIO
0
memType
28
0
address
0
prefetchable
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.2.11
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:3] + 28h
Default: 00000000h
31
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
24
Bit
Range
Default &
Access
0h
RO
31: 0
16.5.2.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:3] + 2Ch
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.2.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:3] + 2Eh
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
12
Bit
Range
15: 0
Default &
Access
0h
RO
August 2015
Document Number: 329676-005US
Description
Subsystem ID (value): PCI Subsystem ID
Intel® Quark™ SoC X1000
Datasheet
459
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.14
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:3] + 30h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
16.5.2.15
0
0
0
0
0
0
0
RSVD
ROM_base_addr
0
28
0
AddrDecodeEn
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:3] + 34h
Default: 00000080h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
RSVD0
0
28
Bit
Range
16.5.2.16
4
1
0
0
0
0
0
0
0
0
value
31
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
Intel® Quark™ SoC X1000
Datasheet
460
INTR_LINE: [B:0, D:20, F:3] + 3Ch
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.2.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:3] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
7: 0
16.5.2.18
Default &
Access
Description
04h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:3] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
Bit
Range
Default &
Access
7: 0
0h
RO
August 2015
Document Number: 329676-005US
Description
MIN_GNT (value): Hardwired to 0
Intel® Quark™ SoC X1000
Datasheet
461
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.19
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:3] + 3Fh
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
value
0
0
16.5.2.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Serial Bus Release Number Register (SBRN)—Offset 60h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
SBRN: [B:0, D:20, F:3] + 60h
Default: 20h
7
4
0
1
0
0
0
0
SBRN
0
16.5.2.21
Bit
Range
Default &
Access
Description
7: 0
20h
RO
Serial Bus Specification Release Number (SBRN): Serial Bus Specification Release
Number.
Frame Length Adjustment Register (FLADJ)—Offset 61h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
FLADJ: [B:0, D:20, F:3] + 61h
Default: 20h
7
4
0
1
0
RSVD0
Bit
Range
Default &
Access
7: 6
0h
RO
Intel® Quark™ SoC X1000
Datasheet
462
0
0
0
0
0
FLADJ
0
Description
RSVD0 (RSVD0): Reserved
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.2.22
Bit
Range
Default &
Access
5: 0
20h
RW
Description
Frame Length Timing Value (FLADJ): Each decimal value change to this register
corresponds to 16 highspeed bit times. The SOF cycle time (number of SOF counter
clock periods to generate a SOF micro-frame length) is equal to 59488 + value in this
field. The default value is decimal 32 (20h), which gives a SOF cycle time of 60000.
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:3] + 80h
Default: 01h
7
4
0
0
0
0
0
0
1
value
0
0
16.5.2.23
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:3] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
0
value
1
16.5.2.24
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMC: [B:0, D:20, F:3] + 82h
Default: F803h
August 2015
Document Number: 329676-005US
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Datasheet
463
Intel® Quark™ SoC X1000—USB 2.0
16.5.2.25
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
1
0
DSI
1
4
aux_curr
1
D1_support
1
8
PME_support
1
12
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
1Fh
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:3] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
0
0
1
0
RSVD
0
4
0
0
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
14: 13
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
15
Intel® Quark™ SoC X1000
Datasheet
464
power_state
Description
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.26
Default &
Access
Description
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:3] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.27
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:3] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.2.28
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
465
Intel® Quark™ SoC X1000—USB 2.0
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:3] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
16.5.2.29
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:3] + A1h
Default: C0h
7
4
1
0
0
0
0
0
0
value
1
0
16.5.2.30
Bit
Range
Default &
Access
Description
7: 0
C0h
RO
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xC0 to point to the USB Legacy Support Extended
Capability Structure
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:3] + A2h
Default: 0100h
Bit
Range
15: 9
Intel® Quark™ SoC X1000
Datasheet
466
0
0
1
0
Default &
Access
0h
RO
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
Description
RSVD0 (RSVD0): Reserved
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.5.2.31
Default &
Access
Description
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:3] + A4h
Default: 00000000h
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
address
0
24
Bit
Range
16.5.2.32
0
0
RSVD0
31
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:3] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
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Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
467
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
16.5.2.33
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:3] + ACh
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
16.5.2.34
0
MSIMask
RSVD0
0
28
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:3] + B0h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
16.5.2.35
Default &
Access
0
value
RSVD0
0
28
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
USB Legacy Support Extended Capability (USBLEGSUP)—Offset C0h
Access Method
Intel® Quark™ SoC X1000
Datasheet
468
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: PCI Configuration Register
(Size: 32 bits)
USBLEGSUP: [B:0, D:20, F:3] + C0h
Default: 00000001h
0
0
0
0
HC_OS_Owned_Semaphore
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
Bit
Range
Default &
Access
31: 25
0h
RO
RSVD0 (RSVD0): Reserved
0b
RW
HC OS Owned Semaphore (HC_OS_Owned_Semaphore): System software sets
this bit to request ownership of the EHCI controller. Ownership is obtained when this bit
reads as one and the HC BIOS Owned Semaphore bit reads as zero.
00h
RO
Reserved (RSVD): Reserved.
16
0b
RW
HC BIOS Owned Semaphore (HC_BIOS_Owned_Semaphore): The BIOS sets this
bit to establish ownership of the EHCI controller. System BIOS will set this bit to a zero
in response to a request for ownership of the EHCI controller by system software.
15: 8
0h
RO
Next EHCI Extended Capability Pointer (NXT_CAP_PTR): This field points to the
PCI configuration space offset of the next extended capability pointer. A value of 00h
indicates the end of the extended capability list.
7: 0
01h
RO
Capability ID (CAP_ID): This field identifies the extended capability. A value of 01h
identifies the capability as Legacy Support. This extended capability requires one
additional 32-bit register for control/status information, and this register is located at
offset EECP+04h.
24
23: 17
16.5.2.36
0
12
CAP_ID
0
16
NXT_CAP_PTR
0
20
HC_BIOS_Owned_Semaphore
0
24
RSVD0
0
28
RSVD
31
Description
USB Legacy Support Control/Status (USBLEGCTLSTS)—Offset C4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
USBLEGCTLSTS: [B:0, D:20, F:3] + C4h
Default: 00000000h
August 2015
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Datasheet
469
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
SMI_USB_ERROR_EN
0
SMI_USB_COMPLETE_EN
0
SMI_PORT_CHANGE_DETECT_EN
0
SMI_FRAME_LIST_ROLLOVER_EN
0
0
SMI_ASYNC_ADVANCE_EN
0
4
SMI_HOST_SYSTEM_ERROR_EN
0
8
RSVD
0
SMI_OS_OWNR_CHANGE_EN
0
SMI_BAR_EN
0
SMI_PCI_CMD_EN
0
SMI_USB_ERROR
0
12
SMI_USB_COMPLETE
0
SMI_PORT_CHANGE_DETECT
0
SMI_FRAME_LIST_ROLLOVER
0
16
SMI_ASYNC_ADVANCE
0
20
SMI_HOST_SYSTEM_ERROR
0
24
RSVD
0
SMI_OS_OWNR_CHANGE
SMI_BAR
0
28
SMI_PCI_CMD
31
Description
31
0b
RW
SMI on BAR (SMI_BAR): This bit is set to one whenever the Base Address Register
(BAR) is written.
30
0b
RW
SMI on PCI Command (SMI_PCI_CMD): This bit is set to one whenever the PCI
Command Register is written.
29
0b
RW
SMI on OS Ownership Change (SMI_OS_OWNR_CHANGE): This bit is set to one
whenever the HC OS Owned Semaphore bit in the USBLEGSUP register transitions from
1 to a 0 or 0 to a 1
00h
RO
Reserved (RSVD): Reserved.
21
0b
RO
SMI on Async Advance (SMI_ASYNC_ADVANCE): Shadow bit of the Interrupt on
Async Advance bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the Interrupt on Async Advance bit in the
USBSTS register.
20
0b
RO
SMI on Host System Error (SMI_HOST_SYSTEM_ERROR): Shadow bit of Host
System Error bit in the USBSTS register, see Section 2.3.2 for definition and effects of
the events associated with this bit being set to a one. To set this bit to a zero, system
software must write a one to the Host System Error bit in the USBSTS register.
19
0b
RO
SMI on Frame List Rollover (SMI_FRAME_LIST_ROLLOVER): Shadow bit of Frame
List Rollover bit in the USBSTS register see Section 2.3.2 for definition. To set this bit to
a zero, system software must write a one to the Frame List Rollover bit in the USBSTS
register.
18
0b
RO
SMI on Port Change Detect (SMI_PORT_CHANGE_DETECT): Shadow bit of Port
Change Detect bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the Port Change Detect bit in the
USBSTS register.
17
0b
RO
SMI on USB Error (SMI_USB_ERROR): Shadow bit of USB Error Interrupt
(USBERRINT) bit in the USBSTS register see Section 2.3.2 for definition. To set this bit
to a zero, system software must write a one to the USB Error Interrupt bit in the
USBSTS register.
16
0b
RO
SMI on USB Complete (SMI_USB_COMPLETE): Shadow bit of USB Interrupt
(USBINT) bit in the USBSTS register see Section 2.3.2 for definition. To set this bit to a
zero, system software must write a one to the USB Interrupt bit in the USBSTS register.
15
0b
RW
SMI on BAR Enable (SMI_BAR_EN): When this bit is one and SMI on BAR is one,
then the host controller will issue an SMI.
14
0b
RW
SMI on PCI Command Enable (SMI_PCI_CMD_EN): When this bit is one and SMI
on PCI Command is one, then the host controller will issue an SMI.
13
0b
RW
SMI on OS Ownership Enable (SMI_OS_OWNR_CHANGE_EN): When this bit is a
one AND the OS Ownership Change bit is one, the host controller will issue an SMI.
28: 22
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
12: 6
00h
RO
Reserved (RSVD): Reserved.
5
0b
RW
SMI on Async Advance Enable (SMI_ASYNC_ADVANCE_EN): When this bit is a
one, and the SMI on Async Advance bit (above) in this register is a one, the host
controller will issue an SMI immediately
4
0b
RW
SMI on Host System Error Enable (SMI_HOST_SYSTEM_ERROR_EN): When this
bit is a one, and the SMI on Host System Error bit (above) in this register is a one, the
host controller will issue an SMI immediately
3
0b
RW
SMI on Frame List Rollover Enable (SMI_FRAME_LIST_ROLLOVER_EN): When
this bit is a one, and the SMI on Frame List Rollover bit (above) in this register is a one,
the host controller will issue an SMI immediately.
2
0b
RW
SMI on Port Change Enable (SMI_PORT_CHANGE_DETECT_EN): When this bit is
a one, and the SMI on Port Change Detect bit (above) in this register is a one, the host
controller will issue an SMI immediately.
1
0b
RW
SMI on USB Error Enable (SMI_USB_ERROR_EN): When this bit is a one, and the
SMI on USB Error bit (above) in this register is a one, the host controller will issue an
SMI immediately.
0
0b
RW
USB SMI Enable (SMI_USB_COMPLETE_EN): When this bit is a one, and the SMI on
USB Complete bit (above) in this register is a one, the host controller will issue an SMI
immediately.
16.5.3
USB OHCI
Table 105.
Summary of PCI Configuration Registers—0/20/4
Offset Start
Offset End
Default
Value
Register ID—Description
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 438
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 439
093Ah
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 439
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 440
0010h
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 440
0C031010h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 441
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 441
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 442
80h
Fh
Fh
“BIST (BIST)—Offset Fh” on page 442
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 443
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 443
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 444
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 444
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 444
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 460
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 460
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 461
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 461
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 462
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 463
01h
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Intel® Quark™ SoC X1000—USB 2.0
Table 105.
Offset Start
Summary of PCI Configuration Registers—0/20/4 (Continued)
Offset End
Default
Value
Register ID—Description
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 463
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 463
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 464
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 465
00h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 465
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 465
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 466
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 466
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 467
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 467
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 485
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 468
00000000h
86h
16.5.3.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:4] + 0h
Default: 8086h
15
12
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
Bit
Range
Default &
Access
8086h
RO
15: 0
16.5.3.2
Description
Vendor ID (value): PCI Vendor ID for Intel
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:4] + 2h
Default: 093Ah
15
0
0
0
8
1
0
0
4
1
0
0
1
1
0
1
0
1
0
value
0
12
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Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
093Ah
RO
15: 0
16.5.3.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:4] + 4h
Default: 0000h
16.5.3.4
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
RSVD
0
8
RSVD0
0
12
IntrDis
15
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
Description
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:4] + 6h
Default: 0010h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
473
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.5.3.5
Default &
Access
0
1
0
0
0
0
RSVD1
0
IntrStatus
0
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:4] + 8h
Default: 0C031010h
0
Intel® Quark™ SoC X1000
Datasheet
474
24
1
1
0
0
20
0
0
0
0
16
0
0
1
1
12
0
0
0
1
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
rev_id
0
progIntf
28
0
classCode
0
subClassCode
31
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.6
Bit
Range
Default &
Access
31: 24
0Ch
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
03h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
10h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:4] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:4] + Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
August 2015
Document Number: 329676-005US
HEADER_TYPE: [B:0, D:20, F:4] + Eh
Intel® Quark™ SoC X1000
Datasheet
475
Intel® Quark™ SoC X1000—USB 2.0
Default: 80h
7
4
0
0
0
multiFnDev
Bit
Range
16.5.3.9
0
0
0
0
0
cfgHdrFormat
1
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:4] + Fh
Default: 00h
7
4
Bit
Range
16.5.3.10
0
0
0
0
0
0
0
comp_code
start_bist
RSVD
0
BIST_capable
0
Default &
Access
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
3: 0
0h
RO
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:4] + 10h
Default: 00000000h
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USB 2.0—Intel® Quark™ SoC X1000
0
0
0
0
0
0
0
0
0
0
0
0
12
0
0
0
0
8
0
0
0
0
16.5.3.11
4
0
0
0
0
0
0
0
0
0
isIO
0
16
memType
0
20
prefetchable
0
24
address
0
28
RSVD
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:4] + 28h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
28
Bit
Range
31: 0
16.5.3.12
Default &
Access
0h
RO
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:4] + 2Ch
Default: 0000h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
477
Intel® Quark™ SoC X1000—USB 2.0
15
12
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
8
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.3.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:4] + 2Eh
Default: 0000h
15
12
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
value
0
8
Bit
Range
Default &
Access
0h
RO
15: 0
16.5.3.14
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:4] + 30h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
RSVD
ROM_base_addr
0
28
0
0
0
0
0
0
0
AddrDecodeEn
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Intel® Quark™ SoC X1000
Datasheet
478
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.15
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:4] + 34h
Default: 00000080h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
Bit
Range
16.5.3.16
0
0
0
0
0
0
value
RSVD0
0
28
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:4] + 3Ch
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.3.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:4] + 3Dh
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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Datasheet
479
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
7: 0
16.5.3.18
Default &
Access
Description
01h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:4] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
0
0
value
0
0
16.5.3.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:4] + 3Fh
Default: 00h
7
4
0
0
0
0
0
0
value
0
16.5.3.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:4] + 80h
Default: 01h
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
7
4
0
0
0
0
0
0
1
value
0
0
16.5.3.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:4] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
value
1
0
16.5.3.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMC: [B:0, D:20, F:4] + 82h
Default: 4803h
0
0
0
0
0
0
0
1
1
version
0
0
PME_clock
0
RSVD
1
DSI
0
4
aux_curr
0
8
D1_support
1
PME_support
0
12
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
August 2015
Document Number: 329676-005US
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Datasheet
481
Intel® Quark™ SoC X1000—USB 2.0
16.5.3.23
Bit
Range
Default &
Access
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Description
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset 84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:4] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
1
0
0
0
power_state
0
0
RSVD
0
4
Description
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
14: 13
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
15
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Datasheet
482
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
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Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.5.3.24
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset
86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:4] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
16.5.3.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset 87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:4] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.26
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:4] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
Bit
Range
Default &
Access
7: 0
05h
RO
August 2015
Document Number: 329676-005US
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Intel® Quark™ SoC X1000
Datasheet
483
Intel® Quark™ SoC X1000—USB 2.0
16.5.3.27
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:4] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
16.5.3.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability structure
in the chain
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:4] + A2h
Default: 0100h
Bit
Range
16.5.3.29
0
0
4
1
0
Default &
Access
0
0
0
0
0
0
0
0
MSIEnable
8
0
multiMsgCap
0
multiMsgEn
0
bit64Cap
12
0
RSVD0
0
perVecMskCap
15
Description
15: 9
0h
RO
RSVD0 (RSVD0): Reserved
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
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Datasheet
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Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:4] + A4h
Default: 00000000h
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
address
0
24
Bit
Range
16.5.3.30
0
0
RSVD0
31
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:4] + A8h
Default: 0000h
15
12
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
8
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
16.5.3.31
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:4] + ACh
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
RSVD0
0
28
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12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
MSIMask
31
Intel® Quark™ SoC X1000
Datasheet
485
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.5.3.32
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:4] + B0h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
RSVD0
0
28
Bit
Range
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
16.6
Memory Mapped Registers
16.6.1
USB Device
Table 106.
Summary of Memory Mapped I/O Registers—BAR0
Offset
Start
Offset End
Default
Value
Register Name (Register Symbol)
0h
3h
“IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)—Offset 0h” on page 489
00000000h
4h
7h
“IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)—Offset 4h” on page 490
00000000h
8h
Bh
“IN Endpoint 0 Buffer Size Register (ep0_in_bufsize_udc_reg)—Offset 8h” on page 492 00000000h
Ch
Fh
“IN Endpoint 0 Maximum Packet Size Register (ep0_in_mpkt_sz_reg)—Offset Ch” on
page 493
14h
17h
“IN Endpoint 0 Data Descriptor Pointer Register (ep0_in_desptr_udc_reg)—Offset 14h”
00000000h
on page 493
1Ch
1Fh
“IN Endpoint 0 Write Confirmation register (for Slave-Only mode)
(ep0_wr_cfrm_udc_reg)—Offset 1Ch” on page 494
00000000h
20h
23h
“IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)—Offset 20h” on page 494
00000000h
24h
27h
“IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)—Offset 24h” on page 495
00000000h
2Bh
“IN Endpoint 1 Buffer Size Register (ep1_in_bufsize_udc_reg)—Offset 28h” on
page 497
00000000h
28h
Intel® Quark™ SoC X1000
Datasheet
486
0
value
31
00000000h
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Table 106.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
2Ch
2Fh
“IN Endpoint 1 Maximum Packet Size Register (ep1_in_mpkt_sz_reg)—Offset 2Ch” on
page 498
34h
37h
“IN Endpoint 1 Data Descriptor Pointer Register (ep1_in_desptr_udc_reg)—Offset 34h”
00000000h
on page 498
3Ch
3Fh
“IN Endpoint 1 Write Confirmation register (for Slave-Only mode)
(ep1_wr_cfrm_udc_reg)—Offset 3Ch” on page 499
00000000h
40h
43h
“IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)—Offset 40h” on page 499
00000000h
44h
47h
“IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)—Offset 44h” on page 500
00000000h
48h
4Bh
“IN Endpoint 2 Buffer Size Register (ep2_in_bufsize_udc_reg)—Offset 48h” on
page 502
00000000h
4Ch
4Fh
“IN Endpoint 2 Maximum Packet Size Register (ep2_in_mpkt_sz_reg)—Offset 4Ch” on
page 503
00000000h
54h
57h
“IN Endpoint 2 Data Descriptor Pointer Register (ep2_in_desptr_udc_reg)—Offset 54h”
00000000h
on page 503
5Ch
5Fh
“IN Endpoint 2 Write Confirmation register (for Slave-Only mode)
(ep2_wr_cfrm_udc_reg)—Offset 5Ch” on page 504
00000000h
60h
63h
“IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)—Offset 60h” on page 504
00000000h
64h
67h
“IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)—Offset 64h” on page 505
00000000h
68h
6Bh
“IN Endpoint 3 Buffer Size Register (ep3_in_bufsize_udc_reg)—Offset 68h” on
page 507
00000000h
6Ch
6Fh
“IN Endpoint 3 Maximum Packet Size Register (ep3_in_mpkt_sz_reg)—Offset 6Ch” on
page 508
00000000h
74h
77h
“IN Endpoint 3 Data Descriptor Pointer Register (ep3_in_desptr_udc_reg)—Offset 74h”
00000000h
on page 508
7Ch
7Fh
“IN Endpoint 3 Write Confirmation register (for Slave-Only mode)
(ep3_wr_cfrm_udc_reg)—Offset 7Ch” on page 509
00000000h
200h
203h
“OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)—Offset 200h” on page 509
00000000h
204h
207h
“OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)—Offset 204h” on page 510
00000100h
208h
20Bh
“OUT Endpoint 0 Receive Packet Frame Number Register (ep0_out_rpf_udc_reg)—
Offset 208h” on page 512
00000000h
20Ch
20Fh
“OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)—Offset 20Ch” on
page 513
00000000h
210h
213h
“OUT Endpoint 0 SETUP Buffer Pointer Register (ep0_subptr_udc_reg)—Offset 210h” on
00000000h
page 513
214h
217h
“OUT Endpoint 0 Data Descriptor Pointer Register (ep0_out_desptr_udc_reg)—Offset
214h” on page 514
00000000h
21Ch
21Fh
“OUT Endpoint 0 Read Confirmation Register for zero-length OUT data (for Slave-Only
mode) (ep0_rd_cfrm_udc_reg)—Offset 21Ch” on page 514
00000000h
220h
223h
“OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)—Offset 220h” on page 515
00000000h
224h
227h
“OUT Endpoint 1 Status Register (ep1_out_sts_udc_reg)—Offset 224h” on page 516
00000100h
228h
22Bh
“OUT Endpoint 1 Receive Packet Frame Number Register (ep1_out_rpf_udc_reg)—
Offset 228h” on page 518
00000000h
22Ch
22Fh
“OUT Endpoint 1 Buffer Size Register (ep1_out_bufsize_udc_reg)—Offset 22Ch” on
page 519
00000000h
230h
233h
“OUT Endpoint 1 SETUP Buffer Pointer Register (ep1_subptr_udc_reg)—Offset 230h” on
00000000h
page 519
234h
237h
“OUT Endpoint 1 Data Descriptor Pointer Register (ep1_out_desptr_udc_reg)—Offset
234h” on page 520
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Document Number: 329676-005US
00000000h
00000000h
Intel® Quark™ SoC X1000
Datasheet
487
Intel® Quark™ SoC X1000—USB 2.0
Table 106.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
23Ch
23Fh
“OUT Endpoint 1 Read Confirmation Register for zero-length OUT data (for Slave-Only
mode) (ep1_rd_cfrm_udc_reg)—Offset 23Ch” on page 520
00000000h
240h
243h
“OUT Endpoint 2 Control Register (ep2_out_ctrl_udc_reg)—Offset 240h” on page 521
00000000h
244h
247h
“OUT Endpoint 2 Status Register (ep2_out_sts_udc_reg)—Offset 244h” on page 522
00000100h
248h
24Bh
“OUT Endpoint 2 Receive Packet Frame Number Register (ep2_out_rpf_udc_reg)—
Offset 248h” on page 524
00000000h
24Ch
24Fh
“OUT Endpoint 2 Buffer Size Register (ep2_out_bufsize_udc_reg)—Offset 24Ch” on
page 525
00000000h
250h
253h
“OUT Endpoint 2 SETUP Buffer Pointer Register (ep2_subptr_udc_reg)—Offset 250h” on
00000000h
page 525
254h
257h
“OUT Endpoint 2 Data Descriptor Pointer Register (ep2_out_desptr_udc_reg)—Offset
254h” on page 526
00000000h
25Ch
25Fh
“OUT Endpoint 2 Read Confirmation Register for zero-length OUT data (for Slave-Only
mode) (ep2_rd_cfrm_udc_reg)—Offset 25Ch” on page 526
00000000h
260h
263h
“OUT Endpoint 3 Control Register (ep3_out_ctrl_udc_reg)—Offset 260h” on page 527
00000000h
264h
267h
“OUT Endpoint 3 Status Register (ep3_out_sts_udc_reg)—Offset 264h” on page 528
00000100h
268h
26Bh
“OUT Endpoint 3 Receive Packet Frame Number Register (ep3_out_rpf_udc_reg)—
Offset 268h” on page 530
00000000h
26Ch
26Fh
“OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)—Offset 26Ch” on
page 531
00000000h
270h
273h
“OUT Endpoint 3 SETUP Buffer Pointer Register (ep3_subptr_udc_reg)—Offset 270h” on
00000000h
page 531
274h
277h
“OUT Endpoint 3 Data Descriptor Pointer Register (ep3_out_desptr_udc_reg)—Offset
274h” on page 532
00000000h
27Ch
27Fh
“OUT Endpoint 3 Read Confirmation Register for zero-length OUT data (for Slave-Only
mode) (ep3_rd_cfrm_udc_reg)—Offset 27Ch” on page 532
00000000h
400h
403h
“Device Configuration Register (d_cfg_udc_reg)—Offset 400h” on page 533
00000020h
404h
407h
“Device Control Register (d_ctrl_udc_reg)—Offset 404h” on page 534
00000400h
408h
40Bh
“Device Status Register (d_sts_udc_reg)—Offset 408h” on page 536
00000000h
40Ch
40Fh
“Device Interrupt Register (d_intr_udc_reg)—Offset 40Ch” on page 537
00000000h
410h
413h
“Device Interrupt Mask Register (d_intr_msk_udc_reg)—Offset 410h” on page 538
00000000h
414h
417h
“Endpoints Interrupt Register (ep_intr_udc_reg)—Offset 414h” on page 539
00000000h
418h
41Bh
“Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)—Offset 418h” on page 539 00000000h
41Ch
41Fh
“Test Mode Register (test_mode_udc_reg)—Offset 41Ch” on page 540
00000000h
420h
423h
“Product Release Number Register (revision_udc_reg)—Offset 420h” on page 541
3234352Ah
500h
503h
“SETUP command address pointer register (udc_desc_addr_udc_reg)—Offset 500h” on
00000000h
page 541
504h
507h
“Physical Endpoint 0 Register (udc_ep_ne_udc_reg_0)—Offset 504h” on page 542
508h
50Bh
“Physical Endpoint 1 Register (udc_ep_ne_udc_reg_1)—Offset 508h” on page 542
00000000h
50Ch
50Fh
“Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)—Offset 50Ch” on page 543
00000000h
510h
513h
“Physical Endpoint 3 Register (udc_ep_ne_udc_reg_3)—Offset 510h” on page 544
00000000h
514h
517h
“Physical Endpoint 4 Register (udc_ep_ne_udc_reg_4)—Offset 514h” on page 545
00000000h
518h
51Bh
“Physical Endpoint 5 Register (udc_ep_ne_udc_reg_5)—Offset 518h” on page 546
00000000h
51Ch
51Fh
“Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)—Offset 51Ch” on page 546
00000000h
Intel® Quark™ SoC X1000
Datasheet
488
00000000h
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Table 106.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
800h + [0803h
511]*4h
“RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])—Offset 800h, Count 512, Stride
00000000h
4h” on page 547
1000h +
1003h
[0-255]*4h
“TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])—Offset 1000h, Count 256,
Stride 4h” on page 548
00000000h
1400h +
1403h
[0-255]*4h
“TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])—Offset 1400h, Count 256,
Stride 4h” on page 548
00000000h
1800h +
1803h
[0-255]*4h
“TxFIFO 2 Array[0-255] (udc_tx_fifo_reg_2_array[0-255])—Offset 1800h, Count 256,
Stride 4h” on page 548
00000000h
1C00h +
1C03h
[0-255]*4h
“TxFIFO 3 Array[0-255] (udc_tx_fifo_reg_3_array[0-255])—Offset 1C00h, Count 256,
Stride 4h” on page 549
00000000h
16.6.1.1
IN Endpoint 0 Control Register (ep0_in_ctrl_udc_reg)—Offset 0h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
RO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): This is an OUT
endpoint field only. These bits are reserved and should be set to zero.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RW
Send Null Packet (null_bit): This bit provides the application with a mechanism to
instruct the USB Device Controller to send a NULL (zero length) packet when no data is
available in the particular endpoint TxFIFO. If this bit is set, when no data is available in
the endpoint TxFIFO, the USB Device Controller sends a NULL packet.
9
0x0
RO
Receive Ready (rrdy): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO corresponding to the same logical endpoint is
empty (Multiple RxFIFO implementation). The application can write CNAK any time
without waiting for a RxFIFO empty condition. The NAK bit is cleared immediately upon
write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Bit (nak): After a SETUP packet, which is decoded by the application, is received
by the core, the core sets the NAK bit for all control IN/OUT endpoints. NAK is also set
after a STALL response for the endpoint (the STALL bit is set in Endpoint Control register
bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: A NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RW
Poll Demand (p): Poll demand from the application. The application can set this bit
after an IN token is received from the endpoint. The application can also set this bit
before an IN token is received for the endpoint, if it has the IN transfer data in advance.
Note: After sending a zero-length or short packet, the application must wait for the next
XFERDONE_TXEMPTY interrupt, before setting up the P bit for the next transfer.
2
0x0
RO
Snoop Mode (sn): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
1
0x0
RW
Flush TxFIFO (f): The application firmware sets this bit to 1 after it has detected a
disconnect/connect on the USB cable, then waits for the IN token endpoint interrupt
before resetting this bit to 0. This flushes the stale data out of the TxFIFO. This bit is
cleared by the core when TDC (Transmit DMA Complete) occurs on this endpoint.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit.
The subsystem returns a STALL handshake for the subsequent transactions of the
stalled endpoint until the USB host issues a Clear_Feature command to clear it. Once
this bit is set, if the subsystem has already returned a STALL handshake to the USB
host, the application firmware cannot clear the S bit to stop the subsystem from sending
the STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
0
16.6.1.2
IN Endpoint 0 Status Register (ep0_in_sts_udc_reg)—Offset 4h
The Endpoint Status register indicates the endpoint status.
Access Method
Intel® Quark™ SoC X1000
Datasheet
490
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RW/1C
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This bit indicates
that the TXFIFO is empty after the DMA transfer has been completed. The application
can use this bit to set the poll bit for the next transfer. The application must first clear
this bit after servicing the interrupt.
26
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint. To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature stall command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RW/1C
Transmit FIFO Empty detected (tx_fifo_empty): This bit indicates that the
Transmit FIFO Empty condition is triggered. Application can use this information to load
the subsequent data into the Transmit FIFO. The application must clear this bit after
writing the data into the Transmit FIFO.
Note: This bit is not used for Isochronous endpoints.
23
0x0
RW/1C
Isochronous IN transaction complete (isoc_xfer_done): This bit indicates that the
isochronous IN transaction for this endpoint is complete. The application can use this
information to program the isochronous IN data for the next microframe. This bit is used
only in Slave-Only mode.
0x0
RO
Receive Packet Size (rx_pkt_size): This is an OUT endpoint field only. These bits are
reserved and should be set to zero.
22:11
10
0x0
RW/1C
Transmit DMA Completion (tdc): Indicates the transmit DMA has completed
transferring a descriptor chain data to the Tx FIFO. After servicing the interrupt, the
application must clear this bit.
9
0x0
RW/1C
Error response on the host bus (he): Error response on the host bus (AHB) when
doing a data transfer, descriptor fetch, or descriptor update for this particular endpoint.
After servicing the interrupt, the application must clear this bit.
8
0x0
RO
August 2015
Document Number: 329676-005US
Receive Address FIFO Empty Status (mrxfifo_empty): This is an OUT endpoint
field only. These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
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491
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.1.3
Default &
Access
Field Name (ID): Description
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it. After servicing the interrupt, the application must clear this
bit.
6
0x0
RW/1C
IN token (in_tok): An IN token has been received by this endpoint. After servicing the
interrupt, application must clear this bit.
5:4
0x0
RO
OUT token (out_tok): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
IN Endpoint 0 Buffer Size Register (ep0_in_bufsize_udc_reg)—Offset
8h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
24
0
0
0
0
Bit
Range
Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_1
0
buff_size_frame_number
28
0
reserved
0
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
17:16
0x0
RW
Isochronous IN Transaction PID (isoc_data_pid): Initial data PID to be sent for a
high-bandwidth isochronous IN transaction. This field is used only in Slave-Only mode.
00: DATA0 PID is sent
01: DATA0 PID is sent
10: DATA1 PID is sent
11: DATA2 PID is sent
15:10
0x0
RO
Buffer Size (buff_size_frame_number): These bits are reserved and should be set
to zero.
9:0
0x0
RW
Buffer Size (buff_size_1): Buffer size required for this endpoint. The application can
program this field to make each endpoints buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Transmit FIFO.
NOTE: the maximum size of the TxFIFO is 1024 32-bit word entries.
31:18
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Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.1.4
IN Endpoint 0 Maximum Packet Size Register (ep0_in_mpkt_sz_reg)—
Offset Ch
This register also specifies the maximum packet size an endpoint should support. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the USB Device Controller register space.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
16.6.1.5
0
4
0
0
0
0
0
0
0
0
0
mpkt_size
buff_size
0
28
Default &
Access
Field Name (ID): Description
31:16
0x0
RO
Buffer Size (buff_size): This is an OUT endpoint field only. These bits are reserved
and should be set to zero.
15:0
0x0
RO
Max Packet Size (mpkt_size): Maximum packet size for the endpoint in bytes. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the corresponding Physical Endpoint Register.
IN Endpoint 0 Data Descriptor Pointer Register
(ep0_in_desptr_udc_reg)—Offset 14h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 14h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
31:0
Default &
Access
0x0
RW
August 2015
Document Number: 329676-005US
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointers.
Intel® Quark™ SoC X1000
Datasheet
493
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.6
IN Endpoint 0 Write Confirmation register (for Slave-Only mode)
(ep0_wr_cfrm_udc_reg)—Offset 1Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
wr_cfrm
0
Bit
Range
Default &
Access
0x0
WO
31:0
16.6.1.7
Field Name (ID): Description
Write Confirmation (for Slave-Only mode) (wr_cfrm): Writing to this register
confirms the IN data into the TxFIFO.
IN Endpoint 1 Control Register (ep1_in_ctrl_udc_reg)—Offset 20h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 20h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
f
0
s
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
RO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): This is an OUT
endpoint field only. These bits are reserved and should be set to zero.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RW
Send Null Packet (null_bit): This bit provides the application with a mechanism to
instruct the USB Device Controller to send a NULL (zero length) packet when no data is
available in the particular endpoint TxFIFO. If this bit is set, when no data is available in
the endpoint TxFIFO, the USB Device Controller sends a NULL packet.
9
0x0
RO
Receive Ready (rrdy): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO corresponding to the same logical endpoint is
empty (Multiple RxFIFO implementation). The application can write CNAK any time
without waiting for a RxFIFO empty condition. The NAK bit is cleared immediately upon
write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Bit (nak): After a SETUP packet, which is decoded by the application, is received
by the core, the core sets the NAK bit for all control IN/OUT endpoints. NAK is also set
after a STALL response for the endpoint (the STALL bit is set in Endpoint Control register
bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: A NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RW
Poll Demand (p): Poll demand from the application. The application can set this bit
after an IN token is received from the endpoint. The application can also set this bit
before an IN token is received for the endpoint, if it has the IN transfer data in advance.
Note: After sending a zero-length or short packet, the application must wait for the next
XFERDONE_TXEMPTY interrupt, before setting up the P bit for the next transfer.
2
0x0
RO
Snoop Mode (sn): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
1
0x0
RW
Flush TxFIFO (f): The application firmware sets this bit to 1 after it has detected a
disconnect/connect on the USB cable, then waits for the IN token endpoint interrupt
before resetting this bit to 0. This flushes the stale data out of the TxFIFO. This bit is
cleared by the core when TDC (Transmit DMA Complete) occurs on this endpoint.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit.
The subsystem returns a STALL handshake for the subsequent transactions of the
stalled endpoint until the USB host issues a Clear_Feature command to clear it. Once
this bit is set, if the subsystem has already returned a STALL handshake to the USB
host, the application firmware cannot clear the S bit to stop the subsystem from sending
the STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
0
16.6.1.8
IN Endpoint 1 Status Register (ep1_in_sts_udc_reg)—Offset 24h
The Endpoint Status register indicates the endpoint status.
Access Method
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
495
Intel® Quark™ SoC X1000—USB 2.0
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 24h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RW/1C
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This bit indicates
that the TXFIFO is empty after the DMA transfer has been completed. The application
can use this bit to set the poll bit for the next transfer. The application must first clear
this bit after servicing the interrupt.
26
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint. To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature stall command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RW/1C
Transmit FIFO Empty detected (tx_fifo_empty): This bit indicates that the
Transmit FIFO Empty condition is triggered. Application can use this information to load
the subsequent data into the Transmit FIFO. The application must clear this bit after
writing the data into the Transmit FIFO.
Note: This bit is not used for Isochronous endpoints.
23
0x0
RW/1C
Isochronous IN transaction complete (isoc_xfer_done): This bit indicates that the
isochronous IN transaction for this endpoint is complete. The application can use this
information to program the isochronous IN data for the next microframe. This bit is used
only in Slave-Only mode.
0x0
RO
Receive Packet Size (rx_pkt_size): This is an OUT endpoint field only. These bits are
reserved and should be set to zero.
22:11
Intel® Quark™ SoC X1000
Datasheet
496
10
0x0
RW/1C
Transmit DMA Completion (tdc): Indicates the transmit DMA has completed
transferring a descriptor chain data to the Tx FIFO. After servicing the interrupt, the
application must clear this bit.
9
0x0
RW/1C
Error response on the host bus (he): Error response on the host bus (AHB) when
doing a data transfer, descriptor fetch, or descriptor update for this particular endpoint.
After servicing the interrupt, the application must clear this bit.
8
0x0
RO
Receive Address FIFO Empty Status (mrxfifo_empty): This is an OUT endpoint
field only. These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.1.9
Default &
Access
Field Name (ID): Description
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it. After servicing the interrupt, the application must clear this
bit.
6
0x0
RW/1C
IN token (in_tok): An IN token has been received by this endpoint. After servicing the
interrupt, application must clear this bit.
5:4
0x0
RO
OUT token (out_tok): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
IN Endpoint 1 Buffer Size Register (ep1_in_bufsize_udc_reg)—Offset
28h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 28h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
24
0
0
0
0
Bit
Range
Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_1
0
buff_size_frame_number
28
0
reserved
0
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
17:16
0x0
RW
Isochronous IN Transaction PID (isoc_data_pid): Initial data PID to be sent for a
high-bandwidth isochronous IN transaction. This field is used only in Slave-Only mode.
00: DATA0 PID is sent
01: DATA0 PID is sent
10: DATA1 PID is sent
11: DATA2 PID is sent
15:10
0x0
RO
Buffer Size (buff_size_frame_number): These bits are reserved and should be set
to zero.
9:0
0x0
RW
Buffer Size (buff_size_1): Buffer size required for this endpoint. The application can
program this field to make each endpoints buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Transmit FIFO.
NOTE: the maximum size of the TxFIFO is 1024 32-bit word entries.
31:18
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
497
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.10
IN Endpoint 1 Maximum Packet Size Register (ep1_in_mpkt_sz_reg)—
Offset 2Ch
This register also specifies the maximum packet size an endpoint should support. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the USB Device Controller register space.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 2Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
16.6.1.11
0
4
0
0
0
0
0
0
0
0
0
mpkt_size
buff_size
0
28
Default &
Access
Field Name (ID): Description
31:16
0x0
RO
Buffer Size (buff_size): This is an OUT endpoint field only. These bits are reserved
and should be set to zero.
15:0
0x0
RO
Max Packet Size (mpkt_size): Maximum packet size for the endpoint in bytes. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the corresponding Physical Endpoint Register.
IN Endpoint 1 Data Descriptor Pointer Register
(ep1_in_desptr_udc_reg)—Offset 34h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 34h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
31:0
Intel® Quark™ SoC X1000
Datasheet
498
Default &
Access
0x0
RW
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointers.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.1.12
IN Endpoint 1 Write Confirmation register (for Slave-Only mode)
(ep1_wr_cfrm_udc_reg)—Offset 3Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 3Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
wr_cfrm
0
Bit
Range
Default &
Access
0x0
WO
31:0
16.6.1.13
Field Name (ID): Description
Write Confirmation (for Slave-Only mode) (wr_cfrm): Writing to this register
confirms the IN data into the TxFIFO.
IN Endpoint 2 Control Register (ep2_in_ctrl_udc_reg)—Offset 40h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 40h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
RO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): This is an OUT
endpoint field only. These bits are reserved and should be set to zero.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RW
Send Null Packet (null_bit): This bit provides the application with a mechanism to
instruct the USB Device Controller to send a NULL (zero length) packet when no data is
available in the particular endpoint TxFIFO. If this bit is set, when no data is available in
the endpoint TxFIFO, the USB Device Controller sends a NULL packet.
9
0x0
RO
Receive Ready (rrdy): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
499
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO corresponding to the same logical endpoint is
empty (Multiple RxFIFO implementation). The application can write CNAK any time
without waiting for a RxFIFO empty condition. The NAK bit is cleared immediately upon
write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Bit (nak): After a SETUP packet, which is decoded by the application, is received
by the core, the core sets the NAK bit for all control IN/OUT endpoints. NAK is also set
after a STALL response for the endpoint (the STALL bit is set in Endpoint Control register
bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: A NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RW
Poll Demand (p): Poll demand from the application. The application can set this bit
after an IN token is received from the endpoint. The application can also set this bit
before an IN token is received for the endpoint, if it has the IN transfer data in advance.
Note: After sending a zero-length or short packet, the application must wait for the next
XFERDONE_TXEMPTY interrupt, before setting up the P bit for the next transfer.
2
0x0
RO
Snoop Mode (sn): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
1
0x0
RW
Flush TxFIFO (f): The application firmware sets this bit to 1 after it has detected a
disconnect/connect on the USB cable, then waits for the IN token endpoint interrupt
before resetting this bit to 0. This flushes the stale data out of the TxFIFO. This bit is
cleared by the core when TDC (Transmit DMA Complete) occurs on this endpoint.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit.
The subsystem returns a STALL handshake for the subsequent transactions of the
stalled endpoint until the USB host issues a Clear_Feature command to clear it. Once
this bit is set, if the subsystem has already returned a STALL handshake to the USB
host, the application firmware cannot clear the S bit to stop the subsystem from sending
the STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
0
16.6.1.14
IN Endpoint 2 Status Register (ep2_in_sts_udc_reg)—Offset 44h
The Endpoint Status register indicates the endpoint status.
Access Method
Intel® Quark™ SoC X1000
Datasheet
500
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 44h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RW/1C
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This bit indicates
that the TXFIFO is empty after the DMA transfer has been completed. The application
can use this bit to set the poll bit for the next transfer. The application must first clear
this bit after servicing the interrupt.
26
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint. To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature stall command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RW/1C
Transmit FIFO Empty detected (tx_fifo_empty): This bit indicates that the
Transmit FIFO Empty condition is triggered. Application can use this information to load
the subsequent data into the Transmit FIFO. The application must clear this bit after
writing the data into the Transmit FIFO.
Note: This bit is not used for Isochronous endpoints.
23
0x0
RW/1C
Isochronous IN transaction complete (isoc_xfer_done): This bit indicates that the
isochronous IN transaction for this endpoint is complete. The application can use this
information to program the isochronous IN data for the next microframe. This bit is used
only in Slave-Only mode.
0x0
RO
Receive Packet Size (rx_pkt_size): This is an OUT endpoint field only. These bits are
reserved and should be set to zero.
22:11
10
0x0
RW/1C
Transmit DMA Completion (tdc): Indicates the transmit DMA has completed
transferring a descriptor chain data to the Tx FIFO. After servicing the interrupt, the
application must clear this bit.
9
0x0
RW/1C
Error response on the host bus (he): Error response on the host bus (AHB) when
doing a data transfer, descriptor fetch, or descriptor update for this particular endpoint.
After servicing the interrupt, the application must clear this bit.
8
0x0
RO
August 2015
Document Number: 329676-005US
Receive Address FIFO Empty Status (mrxfifo_empty): This is an OUT endpoint
field only. These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
501
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.1.15
Default &
Access
Field Name (ID): Description
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it. After servicing the interrupt, the application must clear this
bit.
6
0x0
RW/1C
IN token (in_tok): An IN token has been received by this endpoint. After servicing the
interrupt, application must clear this bit.
5:4
0x0
RO
OUT token (out_tok): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
IN Endpoint 2 Buffer Size Register (ep2_in_bufsize_udc_reg)—Offset
48h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 48h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
24
0
0
0
0
Bit
Range
Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_1
0
buff_size_frame_number
28
0
reserved
0
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
17:16
0x0
RW
Isochronous IN Transaction PID (isoc_data_pid): Initial data PID to be sent for a
high-bandwidth isochronous IN transaction. This field is used only in Slave-Only mode.
00: DATA0 PID is sent
01: DATA0 PID is sent
10: DATA1 PID is sent
11: DATA2 PID is sent
15:10
0x0
RO
Buffer Size (buff_size_frame_number): These bits are reserved and should be set
to zero.
9:0
0x0
RW
Buffer Size (buff_size_1): Buffer size required for this endpoint. The application can
program this field to make each endpoints buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Transmit FIFO.
NOTE: the maximum size of the TxFIFO is 1024 32-bit word entries.
31:18
Intel® Quark™ SoC X1000
Datasheet
502
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.1.16
IN Endpoint 2 Maximum Packet Size Register (ep2_in_mpkt_sz_reg)—
Offset 4Ch
This register also specifies the maximum packet size an endpoint should support. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the USB Device Controller register space.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 4Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
16.6.1.17
0
4
0
0
0
0
0
0
0
0
0
mpkt_size
buff_size
0
28
Default &
Access
Field Name (ID): Description
31:16
0x0
RO
Buffer Size (buff_size): This is an OUT endpoint field only. These bits are reserved
and should be set to zero.
15:0
0x0
RO
Max Packet Size (mpkt_size): Maximum packet size for the endpoint in bytes. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the corresponding Physical Endpoint Register.
IN Endpoint 2 Data Descriptor Pointer Register
(ep2_in_desptr_udc_reg)—Offset 54h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 54h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
31:0
Default &
Access
0x0
RW
August 2015
Document Number: 329676-005US
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointers.
Intel® Quark™ SoC X1000
Datasheet
503
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.18
IN Endpoint 2 Write Confirmation register (for Slave-Only mode)
(ep2_wr_cfrm_udc_reg)—Offset 5Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 5Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
wr_cfrm
0
Bit
Range
Default &
Access
0x0
WO
31:0
16.6.1.19
Field Name (ID): Description
Write Confirmation (for Slave-Only mode) (wr_cfrm): Writing to this register
confirms the IN data into the TxFIFO.
IN Endpoint 3 Control Register (ep3_in_ctrl_udc_reg)—Offset 60h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 60h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
f
0
s
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
RO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): This is an OUT
endpoint field only. These bits are reserved and should be set to zero.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RW
Send Null Packet (null_bit): This bit provides the application with a mechanism to
instruct the USB Device Controller to send a NULL (zero length) packet when no data is
available in the particular endpoint TxFIFO. If this bit is set, when no data is available in
the endpoint TxFIFO, the USB Device Controller sends a NULL packet.
9
0x0
RO
Receive Ready (rrdy): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
504
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the RxFIFO is empty (for single RxFIFO
implementation) or when the RxFIFO corresponding to the same logical endpoint is
empty (Multiple RxFIFO implementation). The application can write CNAK any time
without waiting for a RxFIFO empty condition. The NAK bit is cleared immediately upon
write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Bit (nak): After a SETUP packet, which is decoded by the application, is received
by the core, the core sets the NAK bit for all control IN/OUT endpoints. NAK is also set
after a STALL response for the endpoint (the STALL bit is set in Endpoint Control register
bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: A NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RW
Poll Demand (p): Poll demand from the application. The application can set this bit
after an IN token is received from the endpoint. The application can also set this bit
before an IN token is received for the endpoint, if it has the IN transfer data in advance.
Note: After sending a zero-length or short packet, the application must wait for the next
XFERDONE_TXEMPTY interrupt, before setting up the P bit for the next transfer.
2
0x0
RO
Snoop Mode (sn): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
1
0x0
RW
Flush TxFIFO (f): The application firmware sets this bit to 1 after it has detected a
disconnect/connect on the USB cable, then waits for the IN token endpoint interrupt
before resetting this bit to 0. This flushes the stale data out of the TxFIFO. This bit is
cleared by the core when TDC (Transmit DMA Complete) occurs on this endpoint.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit.
The subsystem returns a STALL handshake for the subsequent transactions of the
stalled endpoint until the USB host issues a Clear_Feature command to clear it. Once
this bit is set, if the subsystem has already returned a STALL handshake to the USB
host, the application firmware cannot clear the S bit to stop the subsystem from sending
the STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
0
16.6.1.20
IN Endpoint 3 Status Register (ep3_in_sts_udc_reg)—Offset 64h
The Endpoint Status register indicates the endpoint status.
Access Method
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
505
Intel® Quark™ SoC X1000—USB 2.0
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 64h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RW/1C
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This bit indicates
that the TXFIFO is empty after the DMA transfer has been completed. The application
can use this bit to set the poll bit for the next transfer. The application must first clear
this bit after servicing the interrupt.
26
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint. To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature stall command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RW/1C
Transmit FIFO Empty detected (tx_fifo_empty): This bit indicates that the
Transmit FIFO Empty condition is triggered. Application can use this information to load
the subsequent data into the Transmit FIFO. The application must clear this bit after
writing the data into the Transmit FIFO.
Note: This bit is not used for Isochronous endpoints.
23
0x0
RW/1C
Isochronous IN transaction complete (isoc_xfer_done): This bit indicates that the
isochronous IN transaction for this endpoint is complete. The application can use this
information to program the isochronous IN data for the next microframe. This bit is used
only in Slave-Only mode.
0x0
RO
Receive Packet Size (rx_pkt_size): This is an OUT endpoint field only. These bits are
reserved and should be set to zero.
22:11
Intel® Quark™ SoC X1000
Datasheet
506
10
0x0
RW/1C
Transmit DMA Completion (tdc): Indicates the transmit DMA has completed
transferring a descriptor chain data to the Tx FIFO. After servicing the interrupt, the
application must clear this bit.
9
0x0
RW/1C
Error response on the host bus (he): Error response on the host bus (AHB) when
doing a data transfer, descriptor fetch, or descriptor update for this particular endpoint.
After servicing the interrupt, the application must clear this bit.
8
0x0
RO
Receive Address FIFO Empty Status (mrxfifo_empty): This is an OUT endpoint
field only. These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.1.21
Default &
Access
Field Name (ID): Description
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it. After servicing the interrupt, the application must clear this
bit.
6
0x0
RW/1C
IN token (in_tok): An IN token has been received by this endpoint. After servicing the
interrupt, application must clear this bit.
5:4
0x0
RO
OUT token (out_tok): This is an OUT endpoint field only. These bits are reserved and
should be set to zero.
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
IN Endpoint 3 Buffer Size Register (ep3_in_bufsize_udc_reg)—Offset
68h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 68h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
24
0
0
0
0
Bit
Range
Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_1
0
buff_size_frame_number
28
0
reserved
0
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
17:16
0x0
RW
Isochronous IN Transaction PID (isoc_data_pid): Initial data PID to be sent for a
high-bandwidth isochronous IN transaction. This field is used only in Slave-Only mode.
00: DATA0 PID is sent
01: DATA0 PID is sent
10: DATA1 PID is sent
11: DATA2 PID is sent
15:10
0x0
RO
Buffer Size (buff_size_frame_number): These bits are reserved and should be set
to zero.
9:0
0x0
RW
Buffer Size (buff_size_1): Buffer size required for this endpoint. The application can
program this field to make each endpoints buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Transmit FIFO.
NOTE: the maximum size of the TxFIFO is 1024 32-bit word entries.
31:18
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
507
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.22
IN Endpoint 3 Maximum Packet Size Register (ep3_in_mpkt_sz_reg)—
Offset 6Ch
This register also specifies the maximum packet size an endpoint should support. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the USB Device Controller register space.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 6Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
16.6.1.23
0
4
0
0
0
0
0
0
0
0
0
mpkt_size
buff_size
0
28
Default &
Access
Field Name (ID): Description
31:16
0x0
RO
Buffer Size (buff_size): This is an OUT endpoint field only. These bits are reserved
and should be set to zero.
15:0
0x0
RO
Max Packet Size (mpkt_size): Maximum packet size for the endpoint in bytes. This
maximum size is used to calculate whether the Receive FIFO has sufficient space to
accept a packet. When changing the maximum packet size for a specific endpoint, the
user must also program the corresponding Physical Endpoint Register.
IN Endpoint 3 Data Descriptor Pointer Register
(ep3_in_desptr_udc_reg)—Offset 74h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 74h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
31:0
Intel® Quark™ SoC X1000
Datasheet
508
Default &
Access
0x0
RW
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointers.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.1.24
IN Endpoint 3 Write Confirmation register (for Slave-Only mode)
(ep3_wr_cfrm_udc_reg)—Offset 7Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 7Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
wr_cfrm
0
Bit
Range
Default &
Access
0x0
WO
31:0
16.6.1.25
Field Name (ID): Description
Write Confirmation (for Slave-Only mode) (wr_cfrm): Writing to this register
confirms the IN data into the TxFIFO.
OUT Endpoint 0 Control Register (ep0_out_ctrl_udc_reg)—Offset
200h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 200h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
16
0
0
0
0
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
sn
20
0
et
0
nak
0
snak
0
rrdy
24
0
cnak
0
null_bit
0
mrx_flush
28
0
reserved
0
close_desc
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
WO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): When the application
wants to flush the endpoint receive FIFO, it must first set the SNAK bit in the Endpoint
Control register. If the receive DMA is in progress, then the core will finish the current
descriptor, terminate the DMA, and flush the data in the endpoint receive FIFO and clear
this bit. The application must clear this bit after the EP receive FIFO is empty, by
checking the MRXFIFO EMPTY bit in the Endpoint Status register.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RO
Send Null Packet (null_bit): This is an IN endpoint field only. These bits are reserved
and should be set to zero.
31:13
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
509
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
Receive Ready (rrdy): If this bit is set by the application, on receiving an OUT packet,
the DMA sends the packet to system memory. This bit is deasserted at the end of packet
if the Descriptor Update bit is set in the Device Control register. This bit is deasserted at
the end of payload if the Descriptor Update bit is deasserted. This bit can be set by the
application at any time. The application cannot clear this bit if the DMA is busy
transferring the data.
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the
RxFIFO is empty (for single RxFIFO implementation) or when the RxFIFO corresponding
to the same logical endpoint is empty (Multiple RxFIFO implementation). The application
can write CNAK any time without waiting for a RxFIFO empty condition. The NAK bit is
cleared immediately upon write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK. (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Handshake Enable (nak): After a SETUP packet, which is decoded by the
application, is received by the core, the core sets the NAK bit for all control IN/OUT
endpoints. NAK is also set after a STALL response for the endpoint (the STALL bit is set
in Endpoint Control register bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: The NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): Endpoint Type (2-bit). The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RO
Poll Demand (p): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
2
0x0
RW
Snoop Mode (sn): Configures the endpoint for Snoop mode. In this mode, the
subsystem does not check the correctness of OUT packets before transferring them to
application memory.
1
0x0
RO
Flush TxFIFO (f): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit. The
subsystem returns a STALL handshake for the subsequent transactions of the stalled
endpoint until the USB host issues a Clear_Feature command to clear it. Once this bit is
set, if the subsystem has already returned a STALL handshake to the USB host, the
application firmware cannot clear the S bit to stop the subsystem from sending the
STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
9
0
16.6.1.26
OUT Endpoint 0 Status Register (ep0_out_sts_udc_reg)—Offset 204h
The Endpoint Status register indicates the endpoint status.
Access Method
Intel® Quark™ SoC X1000
Datasheet
510
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 204h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000100h
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RO
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This is an IN
endpoint field only. These bits are reserved and should be set to zero.
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint .To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature sta command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RO
Transmit FIFO Empty detected (tx_fifo_empty): This is an IN endpoint field only.
These bits are reserved and should be set to zero.
23
0x0
RO
Isochronous IN transaction complete (isoc_xfer_done): This is an IN endpoint
field only. These bits are reserved and should be set to zero.
22:11
0x0
RW
Receive Packet Size (rx_pkt_size): Indicates the number of bytes in the current
receive packet the RxFIFO is receiving. Because the USB host always sends 8 bytes of
SETUP data, these bits do not indicate the receipt of 8 bytes of SETUP data for a SETUP
packet. Rather, these bits indicate the
configuration status (Configuration number [22:19], Interface number [18:15], and
Alternate
Setting number [14:11]). This field is used in slave mode only. In DMA mode, the
application must check the status from the endpoint data descriptor.
10
0x0
RO
Transmit DMA Completion (tdc): This is an IN endpoint field only. These bits are
reserved and should be set to zero.
0x0
RW/1C
System Host Error (he): Error response on the host bus (AHB) when doing a data
transfer, descriptor fetch, or descriptor update for this particular endpoint. After
servicing the interrupt, the application must clear this bit.
26
9
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
511
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.1.27
Default &
Access
Field Name (ID): Description
8
1h
RO
Receive Address FIFO Empty Status (mrxfifo_empty): This bit indicates the empty
status of the endpoint receive address FIFO. This bit is set by the core after the DMA
transfers data to system memory, and there are no new packets received from the USB.
This bit is cleared by the core after receiving a valid packet from the USB.
1: EP RXFIFO is empty
0: EP RXFIFO is not empty
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it.
After servicing the interrupt, the application must clear this bit.
6
0x0
RO
IN token (in_tok): This is an IN endpoint field only. These bits are reserved and
should be set to zero.
5:4
0x0
RW/1C
OUT token. (out_tok): An OUT packet has been received by this endpoint. The
encoding of these two bits
indicates the type of data received. The possible options are:
00: None
01: Received data
10: Received SETUP data (8 bytes)
11: Reserved
(The application must write the same values to clear these bits.)
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
OUT Endpoint 0 Receive Packet Frame Number Register
(ep0_out_rpf_udc_reg)—Offset 208h
This register contains the frame number in which the packet is received. This frame
number information is useful when handling isochronous traffic.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 208h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:18
Intel® Quark™ SoC X1000
Datasheet
512
Default &
Access
0x0
RO
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_frame_number
0
24
reserved
0
28
isoc_data_pid
31
Field Name (ID): Description
reserved: Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RO
Isochronous OUT Transaction PID (isoc_data_pid): Data PID received for a highbandwidth isochronous OUT transaction. This field indicates that the data PID for the
current packet is available in the Receive FIFO. This field is used only in Slave-Only
mode.
00: DATA0 PID is received
01: DATA1 PID is received
10: DATA2 PID is received
11: MDATA PID is received
0x0
RO
Buffer Size/Frame Number (buff_size_frame_number): Frame number in which
the packet is received. For high-speed operation:
[15:14] Reserved
[13:3] Millisecond frame number
[2:0] Microframe number
For full-speed operation:
[15:11] Reserved
[10:0] Millisecond frame number
17:16
15:0
16.6.1.28
OUT Endpoint 0 Buffer Size Register (ep0_out_bufsize_udc_reg)—
Offset 20Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 20Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
Bit
Range
16.6.1.29
0
0
0
4
0
0
0
0
0
0
0
0
0
max_pkt_size
buff_size
0
28
Default &
Access
Field Name (ID): Description
31:16
0x0
RW
Packet Size (buff_size): Buffer size required for this endpoint. The application can
program this field to make each endpoint buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Receive FIFO. This value cannot be
changed dynamically during operation.
NOTE: the maximum size of the RxFIFO is 512 32-bit word entries.
15:0
0x0
RW
Max Packet Size (max_pkt_size): Maximum packet size for the endpoint. This is the
value in bytes. This maximum size is used to calculate whether the Transmit FIFO has
sufficient space to accept a packet. When changing the maximum packet size for a
specific endpoint, the user must also program the corresponding Physical Endpoint
Register.
OUT Endpoint 0 SETUP Buffer Pointer Register
(ep0_subptr_udc_reg)—Offset 210h
Access Method
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Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 210h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
subptr
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
SETUP Buffer Pointer (subptr): Endpoint SETUP buffer pointers are used for SETUP
commands. The Endpoint SETUP Buffer Pointer register is used only in DMA mode.
NOTE: This is applicable only to control endpoints. For all other endpoints this register is
reserved.
31:0
16.6.1.30
OUT Endpoint 0 Data Descriptor Pointer Register
(ep0_out_desptr_udc_reg)—Offset 214h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 214h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
31:0
16.6.1.31
Default &
Access
0x0
RW
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointer.
OUT Endpoint 0 Read Confirmation Register for zero-length OUT data
(for Slave-Only mode) (ep0_rd_cfrm_udc_reg)—Offset 21Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 21Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
rd_cfrm
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Read Confirmation for zero-length OUT data (for Slave-Only mode) (rd_cfrm):
For zero-length OUT data, the application must perform a dummy read from this
register
31:0
16.6.1.32
OUT Endpoint 1 Control Register (ep1_out_ctrl_udc_reg)—Offset
220h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 220h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
WO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): When the application
wants to flush the endpoint receive FIFO, it must first set the SNAK bit in the Endpoint
Control register. If the receive DMA is in progress, then the core will finish the current
descriptor, terminate the DMA, and flush the data in the endpoint receive FIFO and clear
this bit. The application must clear this bit after the EP receive FIFO is empty, by
checking the MRXFIFO EMPTY bit in the Endpoint Status register.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RO
Send Null Packet (null_bit): This is an IN endpoint field only. These bits are reserved
and should be set to zero.
0x0
RW
Receive Ready (rrdy): If this bit is set by the application, on receiving an OUT packet,
the DMA sends the packet to system memory. This bit is deasserted at the end of packet
if the Descriptor Update bit is set in the Device Control register. This bit is deasserted at
the end of payload if the Descriptor Update bit is deasserted. This bit can be set by the
application at any time. The application cannot clear this bit if the DMA is busy
transferring the data.
9
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Bit
Range
Default &
Access
Field Name (ID): Description
8
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the
RxFIFO is empty (for single RxFIFO implementation) or when the RxFIFO corresponding
to the same logical endpoint is empty (Multiple RxFIFO implementation). The application
can write CNAK any time without waiting for a RxFIFO empty condition. The NAK bit is
cleared immediately upon write to CNAK bit. No polling is necessary.
7
0x0
WO
Set NAK. (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Handshake Enable (nak): After a SETUP packet, which is decoded by the
application, is received by the core, the core sets the NAK bit for all control IN/OUT
endpoints. NAK is also set after a STALL response for the endpoint (the STALL bit is set
in Endpoint Control register bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: The NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): Endpoint Type (2-bit). The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RO
Poll Demand (p): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
2
0x0
RW
Snoop Mode (sn): Configures the endpoint for Snoop mode. In this mode, the
subsystem does not check the correctness of OUT packets before transferring them to
application memory.
1
0x0
RO
Flush TxFIFO (f): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit. The
subsystem returns a STALL handshake for the subsequent transactions of the stalled
endpoint until the USB host issues a Clear_Feature command to clear it. Once this bit is
set, if the subsystem has already returned a STALL handshake to the USB host, the
application firmware cannot clear the S bit to stop the subsystem from sending the
STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
0
16.6.1.33
OUT Endpoint 1 Status Register (ep1_out_sts_udc_reg)—Offset 224h
The Endpoint Status register indicates the endpoint status.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 224h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
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Default: 00000100h
Default &
Access
0
0
0
12
0
0
0
0
8
0
0
4
0
1
0
0
0
0
0
0
0
0
0
reserved_3
16
0
out_tok
0
bna
0
in_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
he
0
mrxfifo_empty
0
tdc
0
rx_pkt_size
0
clr_feature_halt
20
0
set_feature_halt
0
24
0
cdc
28
0
reserved_1
0
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RO
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This is an IN
endpoint field only. These bits are reserved and should be set to zero.
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint .To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature sta command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RO
Transmit FIFO Empty detected (tx_fifo_empty): This is an IN endpoint field only.
These bits are reserved and should be set to zero.
23
0x0
RO
Isochronous IN transaction complete (isoc_xfer_done): This is an IN endpoint
field only. These bits are reserved and should be set to zero.
22:11
0x0
RW
Receive Packet Size (rx_pkt_size): Indicates the number of bytes in the current
receive packet the RxFIFO is receiving. Because the USB host always sends 8 bytes of
SETUP data, these bits do not indicate the receipt of 8 bytes of SETUP data for a SETUP
packet. Rather, these bits indicate the
configuration status (Configuration number [22:19], Interface number [18:15], and
Alternate
Setting number [14:11]). This field is used in slave mode only. In DMA mode, the
application must check the status from the endpoint data descriptor.
10
0x0
RO
Transmit DMA Completion (tdc): This is an IN endpoint field only. These bits are
reserved and should be set to zero.
0x0
RW/1C
System Host Error (he): Error response on the host bus (AHB) when doing a data
transfer, descriptor fetch, or descriptor update for this particular endpoint. After
servicing the interrupt, the application must clear this bit.
26
9
8
1h
RO
August 2015
Document Number: 329676-005US
Receive Address FIFO Empty Status (mrxfifo_empty): This bit indicates the empty
status of the endpoint receive address FIFO. This bit is set by the core after the DMA
transfers data to system memory, and there are no new packets received from the USB.
This bit is cleared by the core after receiving a valid packet from the USB.
1: EP RXFIFO is empty
0: EP RXFIFO is not empty
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Bit
Range
16.6.1.34
Default &
Access
Field Name (ID): Description
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it.
After servicing the interrupt, the application must clear this bit.
6
0x0
RO
IN token (in_tok): This is an IN endpoint field only. These bits are reserved and
should be set to zero.
5:4
0x0
RW/1C
OUT token. (out_tok): An OUT packet has been received by this endpoint. The
encoding of these two bits
indicates the type of data received. The possible options are:
00: None
01: Received data
10: Received SETUP data (8 bytes)
11: Reserved
(The application must write the same values to clear these bits.)
3:0
0x0
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
OUT Endpoint 1 Receive Packet Frame Number Register
(ep1_out_rpf_udc_reg)—Offset 228h
This register contains the frame number in which the packet is received. This frame
number information is useful when handling isochronous traffic.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 228h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:18
17:16
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Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_frame_number
0
24
reserved
0
28
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
0x0
RO
Isochronous OUT Transaction PID (isoc_data_pid): Data PID received for a highbandwidth isochronous OUT transaction. This field indicates that the data PID for the
current packet is available in the Receive FIFO. This field is used only in Slave-Only
mode.
00: DATA0 PID is received
01: DATA1 PID is received
10: DATA2 PID is received
11: MDATA PID is received
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
16.6.1.35
Buffer Size/Frame Number (buff_size_frame_number): Frame number in which
the packet is received. For high-speed operation:
[15:14] Reserved
[13:3] Millisecond frame number
[2:0] Microframe number
For full-speed operation:
[15:11] Reserved
[10:0] Millisecond frame number
0x0
RO
15:0
Field Name (ID): Description
OUT Endpoint 1 Buffer Size Register (ep1_out_bufsize_udc_reg)—
Offset 22Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 22Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
buff_size
0
Bit
Range
16.6.1.36
0
0
0
4
0
0
0
0
0
0
0
0
0
max_pkt_size
31
Default &
Access
Field Name (ID): Description
31:16
0x0
RW
Packet Size (buff_size): Buffer size required for this endpoint. The application can
program this field to make each endpoint buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Receive FIFO. This value cannot be
changed dynamically during operation.
NOTE: the maximum size of the RxFIFO is 512 32-bit word entries.
15:0
0x0
RW
Max Packet Size (max_pkt_size): Maximum packet size for the endpoint. This is the
value in bytes. This maximum size is used to calculate whether the Transmit FIFO has
sufficient space to accept a packet. When changing the maximum packet size for a
specific endpoint, the user must also program the corresponding Physical Endpoint
Register.
OUT Endpoint 1 SETUP Buffer Pointer Register
(ep1_subptr_udc_reg)—Offset 230h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 230h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
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Intel® Quark™ SoC X1000—USB 2.0
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
subptr
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
SETUP Buffer Pointer (subptr): Endpoint SETUP buffer pointers are used for SETUP
commands. The Endpoint SETUP Buffer Pointer register is used only in DMA mode.
NOTE: This is applicable only to control endpoints. For all other endpoints this register is
reserved.
31:0
16.6.1.37
OUT Endpoint 1 Data Descriptor Pointer Register
(ep1_out_desptr_udc_reg)—Offset 234h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 234h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
Default &
Access
0x0
RW
31:0
16.6.1.38
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointer.
OUT Endpoint 1 Read Confirmation Register for zero-length OUT data
(for Slave-Only mode) (ep1_rd_cfrm_udc_reg)—Offset 23Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 23Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
rd_cfrm
0
28
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Read Confirmation for zero-length OUT data (for Slave-Only mode) (rd_cfrm):
For zero-length OUT data, the application must perform a dummy read from this
register
31:0
16.6.1.39
OUT Endpoint 2 Control Register (ep2_out_ctrl_udc_reg)—Offset
240h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 240h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
WO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): When the application
wants to flush the endpoint receive FIFO, it must first set the SNAK bit in the Endpoint
Control register. If the receive DMA is in progress, then the core will finish the current
descriptor, terminate the DMA, and flush the data in the endpoint receive FIFO and clear
this bit. The application must clear this bit after the EP receive FIFO is empty, by
checking the MRXFIFO EMPTY bit in the Endpoint Status register.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RO
Send Null Packet (null_bit): This is an IN endpoint field only. These bits are reserved
and should be set to zero.
0x0
RW
Receive Ready (rrdy): If this bit is set by the application, on receiving an OUT packet,
the DMA sends the packet to system memory. This bit is deasserted at the end of packet
if the Descriptor Update bit is set in the Device Control register. This bit is deasserted at
the end of payload if the Descriptor Update bit is deasserted. This bit can be set by the
application at any time. The application cannot clear this bit if the DMA is busy
transferring the data.
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the
RxFIFO is empty (for single RxFIFO implementation) or when the RxFIFO corresponding
to the same logical endpoint is empty (Multiple RxFIFO implementation). The application
can write CNAK any time without waiting for a RxFIFO empty condition. The NAK bit is
cleared immediately upon write to CNAK bit. No polling is necessary.
9
8
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Set NAK. (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Handshake Enable (nak): After a SETUP packet, which is decoded by the
application, is received by the core, the core sets the NAK bit for all control IN/OUT
endpoints. NAK is also set after a STALL response for the endpoint (the STALL bit is set
in Endpoint Control register bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: The NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): Endpoint Type (2-bit). The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RO
Poll Demand (p): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
2
0x0
RW
Snoop Mode (sn): Configures the endpoint for Snoop mode. In this mode, the
subsystem does not check the correctness of OUT packets before transferring them to
application memory.
1
0x0
RO
Flush TxFIFO (f): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit. The
subsystem returns a STALL handshake for the subsequent transactions of the stalled
endpoint until the USB host issues a Clear_Feature command to clear it. Once this bit is
set, if the subsystem has already returned a STALL handshake to the USB host, the
application firmware cannot clear the S bit to stop the subsystem from sending the
STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
7
0
16.6.1.40
OUT Endpoint 2 Status Register (ep2_out_sts_udc_reg)—Offset 244h
The Endpoint Status register indicates the endpoint status.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 244h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000100h
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Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RO
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This is an IN
endpoint field only. These bits are reserved and should be set to zero.
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint .To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature sta command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RO
Transmit FIFO Empty detected (tx_fifo_empty): This is an IN endpoint field only.
These bits are reserved and should be set to zero.
23
0x0
RO
Isochronous IN transaction complete (isoc_xfer_done): This is an IN endpoint
field only. These bits are reserved and should be set to zero.
22:11
0x0
RW
Receive Packet Size (rx_pkt_size): Indicates the number of bytes in the current
receive packet the RxFIFO is receiving. Because the USB host always sends 8 bytes of
SETUP data, these bits do not indicate the receipt of 8 bytes of SETUP data for a SETUP
packet. Rather, these bits indicate the
configuration status (Configuration number [22:19], Interface number [18:15], and
Alternate
Setting number [14:11]). This field is used in slave mode only. In DMA mode, the
application must check the status from the endpoint data descriptor.
10
0x0
RO
Transmit DMA Completion (tdc): This is an IN endpoint field only. These bits are
reserved and should be set to zero.
0x0
RW/1C
System Host Error (he): Error response on the host bus (AHB) when doing a data
transfer, descriptor fetch, or descriptor update for this particular endpoint. After
servicing the interrupt, the application must clear this bit.
26
9
8
1h
RO
Receive Address FIFO Empty Status (mrxfifo_empty): This bit indicates the empty
status of the endpoint receive address FIFO. This bit is set by the core after the DMA
transfers data to system memory, and there are no new packets received from the USB.
This bit is cleared by the core after receiving a valid packet from the USB.
1: EP RXFIFO is empty
0: EP RXFIFO is not empty
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it.
After servicing the interrupt, the application must clear this bit.
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Bit
Range
Default &
Access
0x0
RO
IN token (in_tok): This is an IN endpoint field only. These bits are reserved and
should be set to zero.
5:4
0x0
RW/1C
OUT token. (out_tok): An OUT packet has been received by this endpoint. The
encoding of these two bits
indicates the type of data received. The possible options are:
00: None
01: Received data
10: Received SETUP data (8 bytes)
11: Reserved
(The application must write the same values to clear these bits.)
3:0
0x0
RO
6
16.6.1.41
Field Name (ID): Description
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
OUT Endpoint 2 Receive Packet Frame Number Register
(ep2_out_rpf_udc_reg)—Offset 248h
This register contains the frame number in which the packet is received. This frame
number information is useful when handling isochronous traffic.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 248h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:18
17:16
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20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_frame_number
0
24
reserved
0
28
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
0x0
RO
Isochronous OUT Transaction PID (isoc_data_pid): Data PID received for a highbandwidth isochronous OUT transaction. This field indicates that the data PID for the
current packet is available in the Receive FIFO. This field is used only in Slave-Only
mode.
00: DATA0 PID is received
01: DATA1 PID is received
10: DATA2 PID is received
11: MDATA PID is received
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Bit
Range
Default &
Access
16.6.1.42
Buffer Size/Frame Number (buff_size_frame_number): Frame number in which
the packet is received. For high-speed operation:
[15:14] Reserved
[13:3] Millisecond frame number
[2:0] Microframe number
For full-speed operation:
[15:11] Reserved
[10:0] Millisecond frame number
0x0
RO
15:0
Field Name (ID): Description
OUT Endpoint 2 Buffer Size Register (ep2_out_bufsize_udc_reg)—
Offset 24Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 24Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
buff_size
0
Bit
Range
16.6.1.43
0
0
0
4
0
0
0
0
0
0
0
0
0
max_pkt_size
31
Default &
Access
Field Name (ID): Description
31:16
0x0
RW
Packet Size (buff_size): Buffer size required for this endpoint. The application can
program this field to make each endpoint buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Receive FIFO. This value cannot be
changed dynamically during operation.
NOTE: the maximum size of the RxFIFO is 512 32-bit word entries.
15:0
0x0
RW
Max Packet Size (max_pkt_size): Maximum packet size for the endpoint. This is the
value in bytes. This maximum size is used to calculate whether the Transmit FIFO has
sufficient space to accept a packet. When changing the maximum packet size for a
specific endpoint, the user must also program the corresponding Physical Endpoint
Register.
OUT Endpoint 2 SETUP Buffer Pointer Register
(ep2_subptr_udc_reg)—Offset 250h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 250h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
subptr
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
SETUP Buffer Pointer (subptr): Endpoint SETUP buffer pointers are used for SETUP
commands. The Endpoint SETUP Buffer Pointer register is used only in DMA mode.
NOTE: This is applicable only to control endpoints. For all other endpoints this register is
reserved.
31:0
16.6.1.44
OUT Endpoint 2 Data Descriptor Pointer Register
(ep2_out_desptr_udc_reg)—Offset 254h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 254h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
Default &
Access
0x0
RW
31:0
16.6.1.45
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointer.
OUT Endpoint 2 Read Confirmation Register for zero-length OUT data
(for Slave-Only mode) (ep2_rd_cfrm_udc_reg)—Offset 25Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 25Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
rd_cfrm
0
28
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Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Read Confirmation for zero-length OUT data (for Slave-Only mode) (rd_cfrm):
For zero-length OUT data, the application must perform a dummy read from this
register
31:0
16.6.1.46
OUT Endpoint 3 Control Register (ep3_out_ctrl_udc_reg)—Offset
260h
This register is used to program the endpoint as required by the application.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 260h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
s
0
f
0
p
0
0
sn
0
et
0
nak
0
4
snak
0
8
rrdy
0
12
cnak
0
16
null_bit
0
20
mrx_flush
0
24
reserved
0
28
close_desc
31
Field Name (ID): Description
31:13
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
12
0x0
WO
Receive FIFO Flush for Multiple Receive FIFO (mrx_flush): When the application
wants to flush the endpoint receive FIFO, it must first set the SNAK bit in the Endpoint
Control register. If the receive DMA is in progress, then the core will finish the current
descriptor, terminate the DMA, and flush the data in the endpoint receive FIFO and clear
this bit. The application must clear this bit after the EP receive FIFO is empty, by
checking the MRXFIFO EMPTY bit in the Endpoint Status register.
11
0x0
RO
Close Descriptor Channel (close_desc): Close Descriptor Enhancement is not
supported. These bits are reserved and should be set to zero.
10
0x0
RO
Send Null Packet (null_bit): This is an IN endpoint field only. These bits are reserved
and should be set to zero.
0x0
RW
Receive Ready (rrdy): If this bit is set by the application, on receiving an OUT packet,
the DMA sends the packet to system memory. This bit is deasserted at the end of packet
if the Descriptor Update bit is set in the Device Control register. This bit is deasserted at
the end of payload if the Descriptor Update bit is deasserted. This bit can be set by the
application at any time. The application cannot clear this bit if the DMA is busy
transferring the data.
0x0
WO
Clear NAK (cnak): Used by the application to clear the NAK bit (bit 6). After the
subsystem sets bit 6 (NAK), the application must clear it with a write of 1 to the CNAK
bit. (For example, after the application has decoded the SETUP packet and determined it
is not an invalid command, the application must set the CNAK bit of the control endpoint
to 1 to clear the NAK bit.)The application also must clear the NAK bit whenever the
subsystem sets it. (The subsystem sets it due to the application setting the Stall
bit.)The application can clear this bit only when the
RxFIFO is empty (for single RxFIFO implementation) or when the RxFIFO corresponding
to the same logical endpoint is empty (Multiple RxFIFO implementation). The application
can write CNAK any time without waiting for a RxFIFO empty condition. The NAK bit is
cleared immediately upon write to CNAK bit. No polling is necessary.
9
8
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Set NAK. (snak): Used by the application to set the NAK bit (bit 6 of this register). The
application must not set the NAK bit for an IN endpoint until it has received an IN token
interrupt indicating that the TxFIFO is empty.
6
0x0
RO
NAK Handshake Enable (nak): After a SETUP packet, which is decoded by the
application, is received by the core, the core sets the NAK bit for all control IN/OUT
endpoints. NAK is also set after a STALL response for the endpoint (the STALL bit is set
in Endpoint Control register bit 0).
1: The endpoint responds to the USB host with a NAK handshake.
0: The endpoint responds normally.
Note 1: A SETUP packet is sent to the application regardless of whether the NAK bit is
set.
Note 2: The NAK set on ISOC OUT endpoint rejects the ISOC out data packet.
5:4
0x0
RW
Endpoint Type (et): Endpoint Type (2-bit). The possible options are:
00: Control endpoint
01: Isochronous endpoint
10: Bulk endpoint
11: Interrupt endpoint
3
0x0
RO
Poll Demand (p): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
2
0x0
RW
Snoop Mode (sn): Configures the endpoint for Snoop mode. In this mode, the
subsystem does not check the correctness of OUT packets before transferring them to
application memory.
1
0x0
RO
Flush TxFIFO (f): This is an IN endpoint field only. These bits are reserved and should
be set to zero.
0x0
RW
Stall Handshake (s): On successful reception of a SETUP packet (decoded by the
application), the subsystem clears both IN and OUT Stall bits, and sets both the IN and
OUT NAK bits. The application must check for RxFIFO emptiness before setting the IN
and OUT STALL bit.
For non-SETUP packets, the subsystem clears either IN or out STALL bits only if a STALL
handshake is returned to the USB host, then sets the corresponding NAK bit. The
subsystem returns a STALL handshake for the subsequent transactions of the stalled
endpoint until the USB host issues a Clear_Feature command to clear it. Once this bit is
set, if the subsystem has already returned a STALL handshake to the USB host, the
application firmware cannot clear the S bit to stop the subsystem from sending the
STALL handshake on the endpoint. The host must instead send one of the following
commands to clear the endpoint Halt status:
- Clear Feature (Halt)
- SetConfiguration
- SetInterface.
7
0
16.6.1.47
OUT Endpoint 3 Status Register (ep3_out_sts_udc_reg)—Offset 264h
The Endpoint Status register indicates the endpoint status.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 264h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000100h
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Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
reserved_3
0
out_tok
tx_fifo_empty
isoc_xfer_done
Bit
Range
0
bna
0
in_tok
0
4
he
0
8
mrxfifo_empty
0
12
tdc
0
16
rx_pkt_size
0
clr_feature_halt
20
set_feature_halt
0
24
cdc
0
reserved_1
0
28
xfer_done_txf_empty
31
Field Name (ID): Description
31:29
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
28
0x0
RO
Close Descriptor Channel (cdc): Close Descriptor Enhancement is not supported.
These bits are reserved and should be set to zero.
27
0x0
RO
Transfer Done/Transmit FIFO Empty (xfer_done_txf_empty): This is an IN
endpoint field only. These bits are reserved and should be set to zero.
0x0
RW/1C
Received Set Halt (set_feature_halt): This bit indicates that the Set Feature (EP
HALT) command is received for this endpoint .To stall this endpoint, the application can
set the S bit in Endpoint Control Register. After this, the application clears this RSS bit to
acknowledge the reception of Set Feature sta command. Once this RSS bit is cleared,
core sends the zero-length packet for the Status IN phase of Set Feature command.
Received Set Stall indication is applicable only for Bulk and Interrupt transactions.
25
0x0
RW/1C
Received Clear Halt (clr_feature_halt): This bit indicates that the Clear Feature (EP
HALT) command is received for this endpoint. To continue to stall the endpoint, the
application must set the S bit Endpoint Control Register. After this, the application clears
this RCS bit to acknowledge the reception of clear stall command. Once this bit is
cleared, core sends the zero-length packet for the Status IN phase of clear stall
command. Received Clear Stall indication is applicable only for Bulk and Interrupt
transactions.
24
0x0
RO
Transmit FIFO Empty detected (tx_fifo_empty): This is an IN endpoint field only.
These bits are reserved and should be set to zero.
23
0x0
RO
Isochronous IN transaction complete (isoc_xfer_done): This is an IN endpoint
field only. These bits are reserved and should be set to zero.
22:11
0x0
RW
Receive Packet Size (rx_pkt_size): Indicates the number of bytes in the current
receive packet the RxFIFO is receiving. Because the USB host always sends 8 bytes of
SETUP data, these bits do not indicate the receipt of 8 bytes of SETUP data for a SETUP
packet. Rather, these bits indicate the
configuration status (Configuration number [22:19], Interface number [18:15], and
Alternate
Setting number [14:11]). This field is used in slave mode only. In DMA mode, the
application must check the status from the endpoint data descriptor.
10
0x0
RO
Transmit DMA Completion (tdc): This is an IN endpoint field only. These bits are
reserved and should be set to zero.
0x0
RW/1C
System Host Error (he): Error response on the host bus (AHB) when doing a data
transfer, descriptor fetch, or descriptor update for this particular endpoint. After
servicing the interrupt, the application must clear this bit.
26
9
8
1h
RO
Receive Address FIFO Empty Status (mrxfifo_empty): This bit indicates the empty
status of the endpoint receive address FIFO. This bit is set by the core after the DMA
transfers data to system memory, and there are no new packets received from the USB.
This bit is cleared by the core after receiving a valid packet from the USB.
1: EP RXFIFO is empty
0: EP RXFIFO is not empty
7
0x0
RW/1C
Buffer Not Available (bna): The subsystem sets this bit when the descriptor status is
either Host Busy or DMA Done to indicate that the descriptor was not ready at the time
the DMA tried to access it.
After servicing the interrupt, the application must clear this bit.
August 2015
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
0x0
RO
IN token (in_tok): This is an IN endpoint field only. These bits are reserved and
should be set to zero.
5:4
0x0
RW/1C
OUT token. (out_tok): An OUT packet has been received by this endpoint. The
encoding of these two bits
indicates the type of data received. The possible options are:
00: None
01: Received data
10: Received SETUP data (8 bytes)
11: Reserved
(The application must write the same values to clear these bits.)
3:0
0x0
RO
6
16.6.1.48
Field Name (ID): Description
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
OUT Endpoint 3 Receive Packet Frame Number Register
(ep3_out_rpf_udc_reg)—Offset 268h
This register contains the frame number in which the packet is received. This frame
number information is useful when handling isochronous traffic.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 268h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
0
0
Bit
Range
31:18
17:16
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Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buff_size_frame_number
0
24
reserved
0
28
isoc_data_pid
31
Field Name (ID): Description
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
0x0
RO
Isochronous OUT Transaction PID (isoc_data_pid): Data PID received for a highbandwidth isochronous OUT transaction. This field indicates that the data PID for the
current packet is available in the Receive FIFO. This field is used only in Slave-Only
mode.
00: DATA0 PID is received
01: DATA1 PID is received
10: DATA2 PID is received
11: MDATA PID is received
August 2015
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
16.6.1.49
Buffer Size/Frame Number (buff_size_frame_number): Frame number in which
the packet is received. For high-speed operation:
[15:14] Reserved
[13:3] Millisecond frame number
[2:0] Microframe number
For full-speed operation:
[15:11] Reserved
[10:0] Millisecond frame number
0x0
RO
15:0
Field Name (ID): Description
OUT Endpoint 3 Buffer Size Register (ep3_out_bufsize_udc_reg)—
Offset 26Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 26Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
buff_size
0
Bit
Range
16.6.1.50
0
0
0
4
0
0
0
0
0
0
0
0
0
max_pkt_size
31
Default &
Access
Field Name (ID): Description
31:16
0x0
RW
Packet Size (buff_size): Buffer size required for this endpoint. The application can
program this field to make each endpoint buffers adaptive, providing flexibility in buffer
size when the interface or configuration is changed. This value is in 32-bit words, and
indicates the number of 32-bit word entries in the Receive FIFO. This value cannot be
changed dynamically during operation.
NOTE: the maximum size of the RxFIFO is 512 32-bit word entries.
15:0
0x0
RW
Max Packet Size (max_pkt_size): Maximum packet size for the endpoint. This is the
value in bytes. This maximum size is used to calculate whether the Transmit FIFO has
sufficient space to accept a packet. When changing the maximum packet size for a
specific endpoint, the user must also program the corresponding Physical Endpoint
Register.
OUT Endpoint 3 SETUP Buffer Pointer Register
(ep3_subptr_udc_reg)—Offset 270h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 270h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
531
Intel® Quark™ SoC X1000—USB 2.0
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
subptr
0
28
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
SETUP Buffer Pointer (subptr): Endpoint SETUP buffer pointers are used for SETUP
commands. The Endpoint SETUP Buffer Pointer register is used only in DMA mode.
NOTE: This is applicable only to control endpoints. For all other endpoints this register is
reserved.
31:0
16.6.1.51
OUT Endpoint 3 Data Descriptor Pointer Register
(ep3_out_desptr_udc_reg)—Offset 274h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 274h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
desptr
0
28
Bit
Range
Default &
Access
0x0
RW
31:0
16.6.1.52
Field Name (ID): Description
Descriptor Pointer (desptr): This register contains the data descriptor pointer.
OUT Endpoint 3 Read Confirmation Register for zero-length OUT data
(for Slave-Only mode) (ep3_rd_cfrm_udc_reg)—Offset 27Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 27Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
rd_cfrm
0
28
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Datasheet
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August 2015
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
WO
Read Confirmation for zero-length OUT data (for Slave-Only mode) (rd_cfrm):
For zero-length OUT data, the application must perform a dummy read from this
register
31:0
16.6.1.53
Device Configuration Register (d_cfg_udc_reg)—Offset 400h
This register configures the device. It is only set during initial configuration or when
there is a change in the configuration.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 400h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000020h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
spd
0
sp
0
0
rwkp
0
pi
0
ss
0
dir
0
status
0
status_1
0
4
phy_error_detect
0
8
fs_timeout_calib
0
12
hs_timeout_calib
0
csr_prg
0
halt_status
0
ss_ddr
0
16
set_desc
0
20
lpm_en
0
24
reserved
0
28
lpm_auto
31
Field Name (ID): Description
31:22
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
21
0x0
RO
Link Power Mode Enable (lpm_en): Link Power Mode is not supported. These bits
are reserved and should be set to zero.
20
0x0
RO
Link Power Mode Automatic (lpm_auto): Link Power Mode is not supported. These
bits are reserved and should be set to zero.
19
0x0
RO
Double Data Rate (ss_ddr): ULPI PHY interface is not supported. These bits are
reserved and should be set to zero.
18
0x0
RW
Set Descriptor Request Enable (set_desc): Indicates that the device supports Set
Descriptor requests.
0: The USB Device Controller returns a STALL handshake to the USB host.
1: The SETUP packet for the Set Descriptor request passes to the application.
17
0x0
RW
Dynamic Register Programming (csr_prg): The application can program the USB
Device Controller registers dynamically whenever it has received an interrupt for either
a Set Configuration or a Set Interface request. If this bit is set to 1, the USB Device
Controller returns a NAK handshake during the status IN stage of both the Set
Configuration and Set Interface requests until the application has written 1 to the
CSR_DONE bit 13 of the Device Control Register.
16
0x0
RW
Halt Status (halt_status): This bit indicates whether the USB Device Controller must
respond with a STALL or an ACK handshake when the USB host has issued a
Clear_Feature (ENDPOINT_HALT) request for Endpoint 0. Options are:
0: ACK
1: STALL
15:13
0x0
RW
HS Timeout Counter (hs_timeout_calib): Number of PHY Clocks to the USB Device
Controller Timeout Counter(for HS).The application uses these bits to increase the
timeout value (736 to 848 bit times in high-speed operation), which depends on the PHY
delay in generating a line state condition. The default timeout value is 736 bit times.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
533
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
12:10
0x0
RW
FS Timeout Counter (fs_timeout_calib): Number of PHY Clocks to the USB Device
Controller Timeout Counter(for FS).These three bits indicate the number of PHY clocks
to the USB Device Controller timeout counter. The application uses these bits to increase
the timeout value (16 to 18 bit times in full-speed operation), which depends on the PHY
delay in generating line state condition. The default timeout value is 16 bit times.
9
0x0
RW
PHY Error Detect (phy_error_detect): If the application sets this bit, the device
detects the phy_rxvalid or phy_rxactive input signal to be continuously asserted for 2
ms, indicating PHY error.
8
0x0
RW
Non-zero Control Handshake 1 (status_1): This bit, together with STATUS Bit 7,
provides an option for the USB Device Controller to respond to the USB host with a
STALL or ACK handshake if the USB host has issued a non-zero-length data packet
during the STATUS-OUT stage of a CONTROL transfer.
7
0x0
RW
Non-zero Control Handshake (status): This bit, together with STATUS Bit 8,
provides an option for the USB Device Controller to respond to the USB host with a
STALL or ACK handshake if the USB host has issued a non-zero-length data packet
during the STATUS-OUT stage of a CONTROL transfer.
6
0x0
RO
UTMI Data Bus Direction (dir): This bit indicates if the UTMI data bus interface has to
support a unidirectional or bidirectional interface.
0: Unidirectional interface
1: Bidirectional interface
5
1h
RW
PHY Interface Width (pi): Indicates if the UTMI PHY supports an 8-bit or 16-bit
interface.
0: 16-bit
1: 8-bit.
NOTE: even if this field is writable, only 8bit interface is supported. Writing 0 will lead to
undefined behavior.
4
0x0
RW
Sync Frame Support (ss): Indicates that the Device Supports Sync Frame.
3
0x0
RW
Self-Powered Device (sp): Indicates that the Device is Self-Powered.
2
0x0
RW
Remote Wake Up Capable (rwkp): Indicates that the device is remote wake up
capable.
0x0
RW
Device Speed (spd): This is the expected speed the application programs to the
subsystem. The actual speed the subsystem operates depends on the enumeration
speed (ENUM SPD) of the Device Status register.
00: HS (PHY clock = 60 MHz)
01: FS (PHY clock = 60 MHz)
10: Reserved
11: Reserved
1:0
16.6.1.54
Device Control Register (d_ctrl_udc_reg)—Offset 404h
This register is set at runtime and controls the device after device configuration.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 404h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000400h
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Datasheet
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August 2015
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
rde
res
0
reserved_2
0
du
0
tde
0
bf
0
be
0
the
0
bren
0
sd
0
0
mode
0
4
scale
0
8
devnak
0
12
csr_done
0
16
srx_flush
0
20
reserved_1
0
24
thlen
0
28
brlen
31
Default &
Access
Field Name (ID): Description
31:24
0x0
RW
Threshold Length (thlen): Indicates the number (THLEN + 1) of 32-bit entries in the
RxFIFO before the DMA can start data transfer.
23:16
0x0
RW
Burst Length (brlen): Indicates the length, in 32-bit transfers, of a single burst on the
AHB. The subsystem sends number of 32-bit transfers equal to (BRLEN + 1).
15
0x0
RO
reserved_1: Reserved bits.
These bits are reserved and should be set to zero.
14
0x0
RO
Receive FIFO Flush for Single Receive FIFO (srx_flush): Multiple receive FIFOs are
implemented. These bits are reserved and should be set to zero.
13
0x0
WO
Dynamic Register Programming Done (csr_done): The application uses this bit to
notify the USB Device Controller that the application has completed programming all
required USB Device Controller registers, and the Subsystem can acknowledge the
current Set Configuration or Set Interface command.
12
0x0
RW
Device NAK (devnak): When the application sets this bit, the Subsystem core returns
a NAK handshake to all OUT endpoints. By writing 1 to this bit, the application does not
need to write 1 to the
SNAK bit 7 of each Endpoint Control register.
11
0x0
RW
Scale Down (scale): This bit reduces the timer values inside the USB Device Controller
when running gate-level simulation only. When this bit is set to 1, timer values are
scaled down to reduce simulation time. In Scale-Down mode, the USB Device Controller
detects a USB reset within 150 PHY clock cycles (60-MHz PHY clock, 8-bit UTMI).
Reset this bit to 0 for normal operation.
10
1h
RW
Soft Disconnect (sd): The application software uses this bit to signal the USB Device
Controller to soft-disconnect. When set to 1, this bit causes the device to enter the
disconnected state.
9
0x0
RW
DMA/Slave-Only Mode (mode): Enables the application to dictate the subsystem
operation in either DMA mode (1) or Slave-Only mode (0) operation.
8
0x0
RW
Burst Enable (bren): When this bit is set, transfers on the AHB are split into bursts.
7
0x0
RW
Threshold Enable (the): When this bit is set, a number of quadlets equivalent to the
threshold value is transferred from the RxFIFO to the memory.
6
0x0
RW
Buffer Fill Mode (bf): The DMA is in Buffer Fill mode and transfers data into
contiguous locations pointed to by the buffer address.
5
0x0
RW
System Endianness (be): A value of 1 indicates a big endian system.
4
0x0
RW
Descriptor Update (du): When this bit is set, the DMA updates the descriptor at the
end of each packet processed.
3
0x0
RW
Transmit DMA Enable (tde): 0: disabled
1: enabled
2
0x0
RW
Receive DMA Enable (rde): 0: disabled
1: enabled
1
0x0
RO
reserved_2: Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
535
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
Remote Wakeup Resume (res): To perform a remote wakeup resume the application
sets this bit to 1, then resets it to 0 after 1 ms. The USB Device Controller signals the
USB host to resume the USB bus. However:
The application must first set RWKP bit 2 in the Device Configuration Register, indicating
that the subsystem supports the Remote Wakeup feature.
The host must already have issued a Set Feature request to enable the device Remote
Wakeup feature.
0
16.6.1.55
Device Status Register (d_sts_udc_reg)—Offset 408h
This register reflects status information needed to service some of the interrupts.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 408h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
0
0
0
16
0
0
0
12
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Field Name (ID): Description
0x0
RO
Received SOF Frame Number (ts): For high-speed operation:
[31:21]: Millisecond frame number
[20:18]: Microframe number
For full-speed operation:
[31:29]: Reserved
[28:18]: Millisecond frame number
0x0
RO
Remote Wakeup Status (rmtwkup_feat_sts): Status of Remote wakeup feature
due to Set/Clear Feature (Remotewakeup) command from the host. A value of 1
indicates a Set Feature (Remotewakeup) has been received. A value of 0 indicates Clear
Feature (Remotewakeup) has been received.
Any change to this bit sets an interrupt in bit 7 of Device Interrupt register, if not
masked.
16
0x0
RO
PHY Error (phy_error): Either the phy_rxvalid or phy_rxactive input signal is detected
to be continuously asserted for 2 ms, indicating PHY error. The USB Device Controller
goes to the Suspend state
as a result. When the application serves the early suspend interrupt (ES bit 2 of the
Device
Interrupt register) it also must check this bit to determine if the early suspend interrupt
was
generated due to PHY error detection.
15
0h
RO
Receive Address FIFO Empty Status (rxfifo_empty): Multiple receive FIFOs are
implemented. These bits are reserved and should be set to zero.
31:18
17
Intel® Quark™ SoC X1000
Datasheet
536
Default &
Access
20
0
cfg
0
intf
0
alt
0
susp
24
0
enum_spd
0
phy_error
0
rxfifo_empty
28
0
ts
0
rmtwkup_feat_sts
31
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.1.56
Default &
Access
Field Name (ID): Description
14:13
0x0
RO
Enumerated Speed (enum_spd): These bits hold the speed at which the subsystem
comes up after the speed enumeration. Possible options are:
00 HS: If the SPD is high speed and the subsystem connects to a 2.0 host controller,
then after Speed Enumeration, these bits indicate that the subsystem is operating in
high speed mode.
01 FS: If the expected speed (SPD of the Device Configuration register) is high speed
and the subsystem connects to a 1.1 host controller, then after Speed Enumeration,
these bits indicate that the subsystem is operating in full speed mode.
10 : Reserved
110: Reserved
12
0x0
RO
Suspend Status (susp): This bit is set as long as a Suspend condition is detected on
the USB.
11:8
0x0
RO
Alternate Setting (alt): This 4-bit field represents the alternate setting to which the
above interface is switched.
7:4
0x0
RO
SetInterface Command (intf): This 4-bit field reflects the interface set by the
SetInterface command.
3:0
0x0
RO
SetConfiguration Command (cfg): This 4-bit field reflects the configuration set by
the SetConfiguration command.
Device Interrupt Register (d_intr_udc_reg)—Offset 40Ch
Device interrupts are set when there are system-level events. Interrupts are used by
the application to make system-level decisions. After checking the register, the
application must clear the interrupt by writing a 1?b1 to the correct bit.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 40Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Bit
Range
Default &
Access
0
16
0
0
0
0
12
0
0
0
0
8
0
0
4
0
0
0
0
0
0
0
0
0
0
0
sc
0
si
0
ur
20
0
es
0
us
0
sof
0
enumc
24
0
rmtwkup
0
slpm
0
lpm_tkn
28
0
reserved
0
e_slpm
31
Field Name (ID): Description
31:11
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
10
0x0
RO
LPM Early Sleep (e_slpm): Link Power Mode is not supported. These bits are reserved
and should be set to zero.
9
0x0
RO
LPM Sleep (slpm): Link Power Mode is not supported. These bits are reserved and
should be set to zero.
8
0x0
RO
LPM Transaction (lpm_tkn): Link Power Mode is not supported. These bits are
reserved and should be set to zero.
7
0x0
RW/1C
August 2015
Document Number: 329676-005US
Remote Wakeup (rmtwkup): A Set/Clear Feature (Remote Wakeup) is received by
the core. This bit is set by the core whenever bit 17 of the Device Status Register
changes: HIGH to LOW or LOW to HIGH.
Intel® Quark™ SoC X1000
Datasheet
537
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.1.57
Default &
Access
Field Name (ID): Description
6
0x0
RW/1C
Speed Enumeration Completed (enumc): Speed enumeration is complete.
5
0x0
RW/1C
SOF Token Detected (sof): An SOF token is detected on the USB.
4
0x0
RW/1C
Suspend State (us): A suspend state is detected on the USB for a duration of 3
milliseconds, following the 3 ms Idle State interrupt activity due to an idle state.
3
0x0
RW/1C
USB Reset Detected (ur): NOTE: If the application has not served this interrupt, the
USB Device Controller returns a NAK handshake for all transactions except the 8 SETUP
packet bytes from the USB host.
2
0x0
RW/1C
Idle State Detected (es): An idle state is detected on the USB for a duration of 3 ms.
This interrupt bit is used for the application firmware to finish its job before the
subsystem generates a true suspend (US) interrupt (another 3 ms after the ES
interrupt)
1
0x0
RW/1C
Set_Interface Command Received (si): The device has received a Set_Interface
command.
NOTE: If the application has not served this interrupt, the USB Device Controller returns
a NAK handshake for all transactions except the 8 SETUP packet bytes from the USB
host.
0
0x0
RW/1C
Set_Configuration Command Received (sc): NOTE: If the application has not
served this interrupt, the USB Device Controller returns a NAK handshake for all
transactions except the 8 SETUP packet bytes from the USB host.
Device Interrupt Mask Register (d_intr_msk_udc_reg)—Offset 410h
The device interrupt mask can be set for system-level interrupts using this register.
Programming 1'b1 in the appropriate bit position in the Interrupt Mask register masks
the designated interrupt. Once masked, an interrupt signal does not reach the
application, nor does its interrupt bit get set.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 410h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
24
0
0
0
0
20
0
0
0
Bit
Range
Default &
Access
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
mask1
0
slpm
0
lpm_tkn
28
0
reserved
0
e_slpm
31
Field Name (ID): Description
31:11
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
10
0x0
RO
LPM Early Sleep (e_slpm): Link Power Mode is not supported. These bits are reserved
and should be set to zero.
9
0x0
RO
LPM Sleep (slpm): Link Power Mode is not supported. These bits are reserved and
should be set to zero.
8
0x0
RO
LPM Transaction (lpm_tkn): Link Power Mode is not supported. These bits are
reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0x0
RW
Device Interrupt Mask (mask1): Masks equivalent device interrupt bit in the Device
Interrupt Register.
7:0
16.6.1.58
Endpoints Interrupt Register (ep_intr_udc_reg)—Offset 414h
The Endpoint Interrupt register is used to set endpoint-level interrupts. Since all 4
endpoints are bidirectional, each endpoint has two interrupt bits (one for each
direction). The application needs to clear the interrupt by writing a 1'b1 to the correct
bit after checking the register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 414h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
Bit
Range
31:16
15:0
16.6.1.59
Default &
Access
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
in_ep
out_ep
0
Field Name (ID): Description
0x0
RW/1C
OUT Endpoint Interrupt (out_ep): One bit is associated to one of the 4 supported
OUT endpoint, set when there is an event on that endpoint.
bit0: OUT ED0
bit1: OUT ED1
bit2: OUT ED2
bit3: OUT ED3
bit4-bit15: Reserved
0x0
RW/1C
IN Endpoint Interrupt (in_ep): One bit is associated to one of the 4 supported IN
endpoint, set when there is an event on that endpoint.
bit0: IN ED0
bit1: IN ED1
bit2: IN ED2
bit3: IN ED3
bit4-bit15: Reserved
Endpoints Interrupt Mask Register (ep_intr_msk_udc_reg)—Offset
418h
This register is used to mask endpoint interrupts. A write of 1'b1 to any bit in this
register masks the corresponding endpoint for any possible interrupts. Once masked,
an interrupt signal does not reach the application, nor does its interrupt bit get set.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 418h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
August 2015
Document Number: 329676-005US
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Datasheet
539
Intel® Quark™ SoC X1000—USB 2.0
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Bit
Range
Default &
Access
31:16
15:0
16.6.1.60
0
4
0
0
0
0
0
0
0
0
0
in_ep_mask
out_ep_mask
0
28
Field Name (ID): Description
0h
RW
OUT Endpoint Interrupt Mask (out_ep_mask): Masks the OUT Endpoint Interrupt
Register bits of the equivalent OUT endpoint.
bit0: OUT ED0
bit1: OUT ED1
bit2: OUT ED2
bit3: OUT ED3
bit4-bit15: Reserved
0h
RW
IN Endpoint Interrupt Mask (in_ep_mask): Masks the IN Endpoint Interrupt
Register bits of the equivalent IN endpoint.
bit0: IN ED0
bit1: IN ED1
bit2: IN ED2
bit3: IN ED3
bit4-bit15: Reserved
Test Mode Register (test_mode_udc_reg)—Offset 41Ch
In Test mode, the application can use the AHB to read from a TxFIFO or write to an
RxFIFO using AHB read/write cycles. Test mode is supported only in the Slave-Only
operational mode. In Test mode, only single- DWORD transactions are supported: byte
and word transactions on the AHB are not supported. In non-Test modes, reading from
a TxFIFO or writing to an RxFIFO results in an AHB error response. The application
must never read an empty TxFIFO or write a full RxFIFO even though an AHB error
response is not provided. NOTE: Writing to the RxFIFO in Test mode and enabling the
DMA to transfer the data are not supported.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 41Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:1
0x0
RO
reserved: Reserved bits.
These bits are reserved and should be set to zero.
0
0x0
RW
Test Mode indicator (tstmode): 0: Normal mode
1: Test mode
Intel® Quark™ SoC X1000
Datasheet
540
4
0
tstmode
reserved
0
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.1.61
Product Release Number Register (revision_udc_reg)—Offset 420h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 420h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 3234352Ah
31
0
1
1
24
0
0
1
0
20
0
0
1
1
16
0
1
0
0
12
0
0
1
1
8
0
1
0
1
4
0
0
1
0
0
1
0
1
0
release_id
0
28
Bit
Range
31:0
16.6.1.62
Default &
Access
Field Name (ID): Description
Product Release Number (release_id): This field indicates the ASCII characters of
3234352Ah the four-digit release number in hexadecimal format. For example, 32_34_35_ 2A
represents 2.45* in ASCII character, where * is an alphabetic character (for example, a,
RO
b, or c) that represents a update to the release, which does not impact the RTL source.
SETUP command address pointer register (udc_desc_addr_udc_reg)—
Offset 500h
NOTE: The SETUP command address pointer register is not writable and returns 0 when
read because the SETUP command address pointer is hardcoded to xFFF0.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 500h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
dev_desc_addr_ptr
0
28
Bit
Range
Default &
Access
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
su_cmd_addr_ptr
31
Field Name (ID): Description
31:16
0x0
RO
Device Descriptor Address Pointer (dev_desc_addr_ptr): Device Descriptor
Address Pointer
15:0
0x0
RO
SETUP Command Address Pointer (su_cmd_addr_ptr): SETUP Command Address
Pointer
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
541
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.63
Physical Endpoint 0 Register (udc_ep_ne_udc_reg_0)—Offset 504h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 504h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
max_pkt_size
Bit
Range
16.6.1.64
0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
Physical Endpoint 1 Register (udc_ep_ne_udc_reg_1)—Offset 508h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 508h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
542
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
0
0
0
0
0
0
0
max_pkt_size
Bit
Range
16.6.1.65
0
0
0
0
0
Default &
Access
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
Physical Endpoint 2 Register (udc_ep_ne_udc_reg_2)—Offset 50Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 50Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
max_pkt_size
0
Bit
Range
31:30
Default &
Access
0x0
RW
August 2015
Document Number: 329676-005US
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ep_num
0
ep_dir
24
0
ep_type
0
cfg
0
intf
28
0
reserved
0
alt
31
Field Name (ID): Description
reserved: Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
543
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.1.66
Default &
Access
Field Name (ID): Description
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
Physical Endpoint 3 Register (udc_ep_ne_udc_reg_3)—Offset 510h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 510h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
max_pkt_size
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
Intel® Quark™ SoC X1000
Datasheet
544
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.1.67
Default &
Access
Field Name (ID): Description
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
Physical Endpoint 4 Register (udc_ep_ne_udc_reg_4)—Offset 514h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 514h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
max_pkt_size
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
August 2015
Document Number: 329676-005US
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
Intel® Quark™ SoC X1000
Datasheet
545
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.68
Physical Endpoint 5 Register (udc_ep_ne_udc_reg_5)—Offset 518h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 518h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
0
0
0
0
max_pkt_size
Bit
Range
16.6.1.69
0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
Physical Endpoint 6 Register (udc_ep_ne_udc_reg_6)—Offset 51Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 51Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
546
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
0
0
0
0
0
0
0
max_pkt_size
Bit
Range
16.6.1.70
0
0
0
0
0
Default &
Access
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
ep_num
0
8
ep_dir
0
12
ep_type
0
16
cfg
0
20
intf
0
24
reserved
0
28
alt
31
Field Name (ID): Description
31:30
0x0
RW
reserved: Reserved bits.
These bits are reserved and should be set to zero.
29:19
0x0
RW
Maximum Packet Size (max_pkt_size): NOTE: In full-speed mode operation,
application firmware must program the maximum packet size of default endpoint 0 in
accordance with the value defined in USB 2.0 specification
18:15
0x0
RW
Alternate Setting (alt): Alternate setting to which this endpoint belongs.
14:11
0x0
RW
Interface Number (intf): Interface number to which this endpoint belongs.
10:7
0x0
RW
Configuration Number (cfg): Configuration number to which this endpoint belongs
6:5
0x0
RW
Endpoint Type (ep_type): The possible options are:
00: Control
01: Isochronous
10: Bulk
11: Interrupt
4
0x0
RW
Endpoint Direction (ep_dir): 0: OUT
1: IN
3:0
0x0
RW
Logical Endpoint Number (ep_num): Logical Endpoint Number
RxFIFO Array[0-511] (udc_rx_fifo_reg_array[0-511])—Offset 800h,
Count 512, Stride 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-511]: [BAR0] + 800h + [0-511]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
rx_fifo
0
28
Bit
Range
31:0
Default &
Access
0x0
RW
August 2015
Document Number: 329676-005US
Field Name (ID): Description
Receive FIFO (rx_fifo): Receive FIFO
Intel® Quark™ SoC X1000
Datasheet
547
Intel® Quark™ SoC X1000—USB 2.0
16.6.1.71
TxFIFO 0 Array[0-255] (udc_tx_fifo_reg_0_array[0-255])—Offset
1000h, Count 256, Stride 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-255]: [BAR0] + 1000h + [0-255]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
tx_fifo
0
Bit
Range
Default &
Access
0x0
RW
31:0
16.6.1.72
Field Name (ID): Description
Transmit FIFO 0 (tx_fifo): Transmit FIFO 0
TxFIFO 1 Array[0-255] (udc_tx_fifo_reg_1_array[0-255])—Offset
1400h, Count 256, Stride 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-255]: [BAR0] + 1400h + [0-255]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
tx_fifo
0
28
Bit
Range
31:0
16.6.1.73
Default &
Access
0x0
RW
Field Name (ID): Description
Transmit FIFO 1 (tx_fifo): Transmit FIFO 1
TxFIFO 2 Array[0-255] (udc_tx_fifo_reg_2_array[0-255])—Offset
1800h, Count 256, Stride 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-255]: [BAR0] + 1800h + [0-255]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
548
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
tx_fifo
0
28
Bit
Range
Default &
Access
0x0
RW
31:0
16.6.1.74
Field Name (ID): Description
Transmit FIFO 2 (tx_fifo): Transmit FIFO 2
TxFIFO 3 Array[0-255] (udc_tx_fifo_reg_3_array[0-255])—Offset
1C00h, Count 256, Stride 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-255]: [BAR0] + 1C00h + [0-255]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:2] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
tx_fifo
0
28
Bit
Range
31:0
Default &
Access
0x0
RW
Field Name (ID): Description
Transmit FIFO 3 (tx_fifo): Transmit FIFO 3
16.6.2
USB EHCI
Table 107.
Summary of Memory Mapped I/O Registers—BAR0
Offset
Start
Offset End
Default
Value
Register Name (Register Symbol)
0h
3h
“Host Controller Interface Version Number and Capability Registers Length
(HCCAPBASE)—Offset 0h” on page 550
01000010h
4h
7h
“Host Controller Structural Parameters (HCSPARAMS)—Offset 4h” on page 550
00001212h
8h
Bh
“Host Controller Capability Parameters (HCCPARAMS)—Offset 8h” on page 552
0000C012h
10h
13h
“USB Command (USBCMD)—Offset 10h” on page 553
00080000h
14h
17h
“USB Status (USBSTS)—Offset 14h” on page 555
00001000h
18h
1Bh
“USB Interrupt Enable (USBINTR)—Offset 18h” on page 557
00000000h
1Ch
1Fh
“USB Frame Index (FRINDEX)—Offset 1Ch” on page 558
00000000h
20h
23h
“4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)—Offset 20h” on page 559
00000000h
24h
27h
“Periodic Frame List Base Address (PERIODICLISTBASE)—Offset 24h” on page 559
00000000h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
549
Intel® Quark™ SoC X1000—USB 2.0
Table 107.
Offset
Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register Name (Register Symbol)
28h
2Bh
“Asynchronous List Address (ASYNCLISTADDR)—Offset 28h” on page 560
00000000h
50h
53h
“Configure Flag (CONFIGFLAG)—Offset 50h” on page 560
00000000h
54h + [01]*4h
57h
“Port Status/Control[0-1] (PORTSC[0-1])—Offset 54h, Count 2, Stride 4h” on page 561 00002000h
90h
93h
“Programmable Microframe Base Value (INSNREG00)—Offset 90h” on page 564
00000000h
94h
97h
“Programmable Packet Buffer OUT/IN Thresholds (INSNREG01)—Offset 94h” on
page 565
00200020h
98h
9Bh
“Programmable Packet Buffer Depth (INSNREG02)—Offset 98h” on page 565
00000080h
9Ch
9Fh
“Programmable Controller Settings (INSNREG03)—Offset 9Ch” on page 566
00002001h
A0h
A3h
“Programmable Controller Settings (INSNREG04)—Offset A0h” on page 567
00000000h
A4h
A7h
“UTMI Configuration (INSNREG05)—Offset A4h” on page 568
00001000h
16.6.2.1
Host Controller Interface Version Number and Capability Registers
Length (HCCAPBASE)—Offset 0h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 01000010h
0
0
0
0
0
1
20
0
0
0
0
16
0
0
0
0
12
0
0
0
Bit
Range
31:16
15:8
7:0
16.6.2.2
0
8
0
0
0
0
4
0
0
0
1
0
0
0
0
0
caplength
0
24
hciversion
0
28
reserved_15_8
31
Default &
Access
Field Name (ID): Description
0100h
RO
Host Controller Interface Version Number (hciversion): This is a two-byte register
containing a BCD encoding of the EHCI revision number supported by this host
controller. The most significant byte of this register represents a major revision and the
least significant byte is the minor revision.
0h
RO
010h
RO
reserved_15_8: Reserved bits.
These bits are reserved and should be set to zero.
Capability Registers Length (caplength): This register is used as an offset to add to
register base to find the beginning of the Operational Register Space.
Host Controller Structural Parameters (HCSPARAMS)—Offset 4h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
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Datasheet
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USB 2.0—Intel® Quark™ SoC X1000
Default: 00001212h
Bit
Range
0
Default &
Access
0
0
16
0
0
0
0
12
0
0
0
1
8
0
0
1
0
4
0
0
0
1
0
0
0
1
0
n_ports
20
0
ppc
0
reserved_6_5
0
port_route_rules
0
n_pcc
24
0
n_cc
0
p_indicator
0
reserved_19_17
28
0
reserved_31_24
0
debug_port_number
31
Field Name (ID): Description
31:24
0h
RO
reserved_31_24: Reserved bits.
These bits are reserved and should be set to zero.
23:20
0h
RO
Debug Port Number (debug_port_number): This register identifies which of the
host controller ports is the debug port. The value is the port number (one-based) of the
debug port. A non-zero value in this field indicates the presence of a debug port. The
value in this register must not be greater than N_PORTS.
NOTE: Debug Port is not supported
19:17
000b
RO
reserved_19_17: Reserved bits.
These bits are reserved and should be set to zero.
0b
RO
Port Indicator (p_indicator): This bit indicates whether the ports support port
indicator control. When this bit is a one, the port status and control registers include a
read/writeable field for controlling the state of the port indicator.
NOTE: Port Indicator is not supported
1h
RO
Number of Companion Controllers (n_cc): This field indicates the number of
companion controllers associated with this USB 2.0 host controller. A zero in this field
indicates there are no companion host controllers. Port-ownership hand-off is not
supported. Only high-speed devices are supported on the host controller root ports.
A value larger than zero in this field indicates there are companion USB 1.1 host
controller(s). Port-ownership hand-offs are supported. High, Full- and Low-speed
devices are supported on the host controller root ports.
2h
RO
Number of Ports per Companion Controller (n_pcc): This field indicates the
number of ports supported per companion host controller. It is used to indicate the port
routing configuration to system software.
For example, if N_PORTS has a value of 6 and N_CC has a value of 2 then N_PCC could
have a value of 3. The convention is that the first N_PCC ports are assumed to be routed
to companion controller 1, the next N_PCC ports to companion controller 2, etc. In the
previous example, the N_PCC could have been 4, where the first 4 are routed to
companion controller 1 and the last two are routed to companion controller 2. The
number in this field must be consistent with N_PORTS and N_CC.
7
0b
RO
Port Routing Rules (port_route_rules): This field indicates the method used by this
implementation for how all ports are mapped to companion controllers. The value of this
field has the following interpretation:
0: The first N_PCC ports are routed to the lowest numbered function companion host
controller, the next N_PCC port are routed to the next lowest function companion
controller, and so on.
1: The port routing is explicitly enumerated by the first N_PORTS elements of the HCSPPORTROUTE array.
6:5
00b
RO
reserved_6_5: Reserved bits.
These bits are reserved and should be set to zero.
1b
RO
Port Power Control (ppc): This field indicates whether the host controller
implementation includes port power control. A one in this bit indicates the ports have
port power switches. A zero in this bit indicates the port do not have port power
switches. The value of this field affects the functionality of the Port Power field in each
port status and control register.
NOTE: Port Power Control is supported.
16
15:12
11:8
4
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Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
2h
RO
Number of Physical Downstream Ports (n_ports): This field specifies the number
of physical downstream ports implemented on this host controller. The value of this field
determines how many port registers are addressable in the Operational Register Space.
Valid values are in the range of 1 to F. A zero in this field is undefined.
3:0
16.6.2.3
Host Controller Capability Parameters (HCCPARAMS)—Offset 8h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 0000C012h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
0
frame_list_flag
0
0
address_64bit_cap
0
4
reserved_3
0
8
async_schedule_park_cap
0
12
isoc_schedule_threshold
0
16
eecp
0
20
reserved_16
0
24
reserved_31_18
0
28
link_power_mgmt_cap
31
Field Name (ID): Description
31:18
0h
RO
reserved_31_18: Reserved bits.
These bits are reserved and should be set to zero.
17
0h
RO
Link Power Management Capability (link_power_mgmt_cap): NOTE: Link Power
Management is not supported.
16
0h
RO
reserved_16: Reserved bits.
These bits are reserved and should be set to zero.
C0h
RO
EHCI Extended Capabilities Pointer (eecp): This optional field indicates the
existence of a capabilities list. A value of 00h indicates no extended capabilities are
implemented. A non-zero value in this register indicates the offset in PCI configuration
space of the first EHCI extended capability. The pointer value must be 40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of
device.
NOTE: EHCI Extended Capabilities is supported.
7:4
1h
RO
Isochronous Scheduling Threshold (isoc_schedule_threshold): This field
indicates, relative to the current position of the executing host controller, where
software can reliably update the isochronous schedule.
When bit [7] is zero, the value of the least significant 3 bits indicates the number of
micro-frames a host controller can hold a set of isochronous data structures (one or
more) before flushing the state.
When bit [7] is a one, then host software assumes the host controller may cache an
isochronous data structure for an entire frame.
3
0h
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
15:8
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RO
Async Schedule Park Capability (async_schedule_park_cap): If this bit is set to a
one, then the host controller supports the park feature for high-speed queue heads in
the Asynchronous Schedule and he feature can be disabled or enabled and set to a
specific level by using the Asynchronous Schedule Park Mode Enable and Asynchronous
Schedule Park Mode Count fields in the USBCMD register.
NOTE: Async Schedule Park capability is not supported.
1h
RO
Programmable Frame List Flag (frame_list_flag): If this bit is set to a zero, then
system software must use a frame list length of 1024 elements with this host controller
and the USBCMD register Frame List Size field is a read-only register.
If set to a one, then system software can specify and use a smaller frame list and
configure the host controller via the USBCMD register Frame List Size field. The frame
list must always be aligned on a 4K page boundary. This requirement ensures that the
frame list is always physically contiguous.
NOTE: Programmable Frame List Flag is supported.
0h
RO
64-bit Addressing Capability (address_64bit_cap): This field documents the
addressing range capability of this implementation.
The value of this field determines whether software should use the data structures.
Values for this field have the following interpretation:
0: data structures using 32-bit address memory pointers
1: data structures using 64-bit address memory pointers
NOTE: 64-bit Addressing is not supported
2
1
0
16.6.2.4
USB Command (USBCMD)—Offset 10h
This register indicates the command to be executed by the serial bus host controller.
Writing to the register causes a command to be executed.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 10h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00080000h
Bit
Range
31:28
Default &
Access
0h
RO
August 2015
Document Number: 329676-005US
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
run_stop
0
hcreset
0
0
frame_list_size
0
async_schedule_enable
0
periodic_schedule_enable
0
light_hcreset
host_initiated_resume_duration
0
4
intr_on_async_advance_drbell
0
8
async_schedule_park_mode_cnt
0
12
reserved_10
0
16
async_schedule_park_mode_enable
0
20
reserved_15_12
0
24
reserved_31_28
0
28
intr_threshold_ctrl
31
Field Name (ID): Description
reserved_31_28: Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
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Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RO
Host Initiated Resume Duration (host_initiated_resume_duration): If the Link
Power Management Capability bit in the HCCPARAMS register is set to one then this bit
is R/W; otherwise RO and not functional.
NOTE: Link Power Management is not supported.
23:16
08h
RW
Interrupt Threshold Control (intr_threshold_ctrl): This field is used by system
software to select the maximum rate at which the host controller will issue interrupts. If
software writes an invalid value to this register, the results are undefined. Allowed
values are:
00: Reserved
01: 1 micro-frame
02: 2 micro-frames
04: 4 micro-frames
08: 8 micro-frames (default, equates to 1ms)
10: 16 micro-frames (2ms)
20: 32 micro-frames (4ms)
40: 64 micro-frames (8ms)
Any other value in this register yields undefined results. Software modifications to this
bit while HCHalted bit is equal to zero results in undefined behavior.
15:12
0h
RO
reserved_15_12: Reserved bits.
These bits are reserved and should be set to zero.
11
0h
RO
Asynchronous Schedule Park Mode Enable
(async_schedule_park_mode_enable): If the Asynchronous Park Capability bit in
the HCCPARAMS register is a one, then this bit defaults to a 1 and is R/W. Otherwise the
bit must be a zero and is RO. Software uses this bit to enable or disable Park mode.
When this bit is one, Park mode is enabled. When this bit is a zero, Park mode is
disabled.
NOTE: Asynchronous Park Capability is not supported.
10
0h
RO
reserved_10: Reserved bits.
These bits are reserved and should be set to zero.
0h
RO
Asynchronous Schedule Park Mode Count (async_schedule_park_mode_cnt):
If the Asynchronous Park Capability bit in the HCCPARAMS register is a one, then this
field defaults to 3 and is R/W. Otherwise it defaults to zero and is RO. It contains a count
of the number of successive transactions the host controller is allowed to execute from a
high-speed queue head on the Asynchronous schedule before continuing traversal of the
Asynchronous schedule. Valid values are 1h to 3h. Software must not write a zero to this
bit when Park Mode Enable is a one as this will result in undefined behavior.
NOTE: Asynchronous Park Capability is not supported.
0h
RW
Light Host Controller Reset (light_hcreset): This control bit allows the driver to
reset the EHCI controller without affecting the state of the ports or the relationship to
the companion host controllers. For example, the PORSTC registers should not be reset
to their default values and the CF bit setting should not go to zero (retaining port
ownership relationships).A host software read of this bit as zero indicates the Light Host
Controller Reset has completed and it is safe for host software to re-initialize the host
controller. A host software read of this bit as a one indicates the Light Host Controller
Reset has not yet completed. If not implemented a read of this field will always return a
zero.
NOTE: this control bit is supported and resets the EHCI List Processor Master Controller
Unit.
6
0h
RW
Interrupt on Async Advance Doorbell (intr_on_async_advance_drbell): This bit
is used as a doorbell by software to tell the host controller to issue an interrupt the next
time it advances asynchronous schedule.
Software must write a 1 to this bit to ring the doorbell. When the host controller has
evicted all appropriate cached schedule state, it sets the Interrupt on Async Advance
status bit in the USBSTS register. If the Interrupt on Async Advance Enable bit in the
USBINTR register is a one then the host controller will assert an interrupt at the next
interrupt threshold. The host controller sets this bit to a zero after it has set the
Interrupt on Async Advance status bit in the USBSTS register to a one.
Software should not write a one to this bit when the asynchronous schedule is disabled.
Doing so will yield undefined results.
5
0h
RW
Asynchronous Schedule Enable (async_schedule_enable): This bit controls
whether the host controller skips processing the Asynchronous Schedule. Values mean:
0: Do not process the Asynchronous Schedule
1: Use the ASYNCLISTADDR register to access the Asynchronous Schedule
27:24
9:8
7
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Datasheet
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August 2015
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USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
4
3:2
1
0
16.6.2.5
Field Name (ID): Description
0h
RW
Periodic Schedule Enable (periodic_schedule_enable): This bit controls whether
the host controller skips processing the Periodic Schedule. Values mean:
0: Do not process the Periodic Schedule
1: Use the PERIODICLISTBASE register to access the Periodic Schedule
0h
RW
Frame List Size (frame_list_size): This field is RW only if Programmable Frame List
Flag in the HCCPARAMS registers is set to a one. This field specifies the size of the frame
list. The size the frame list controls which bits in the Frame Index Register should be
used for the Frame List Current index. Values mean:
00: 1024 elements (4096) Default value
01: 512 elements (2048 )
10: 256 elements (1024 ) for resource-constrained environments
11: Reserved
0h
RW
Host Controller Reset (hcreset): This control bit is used by software to reset host
controller.
The effects of this on Root Hub registers are similar to a Chip Hardware Reset. When
software writes a one to this bit, the Host Controller resets its internal pipelines, timers,
counters, state machines, etc. to their initial value. Any transaction currently in progress
on USB is immediately terminated. A USB reset is not driven on downstream ports.
PCI Configuration registers are not affected by this reset.
All operational registers, including port registers and port state machines are set to their
initial values. Port ownership reverts to the companion host controller(s).
This bit is set to zero by the Host Controller when the reset process is complete.
Software cannot terminate the reset process early by writing a zero to this register.
Software should not set this bit to a one when the HCHalted bit in the USBSTS register
is a zero. Attempting to reset an actively running host controller will result in undefined
behavior.
0h
RW
Run/Stop bit (run_stop): 1: Run
0: Stop
When set to a 1, the Host Controller proceeds with execution of the schedule. The Host
Controller continues execution as long as this bit is set to a 1. When this bit is set to 0,
the Host Controller completes the current and any actively pipelined transactions on the
USB and then halts. The Host Controller must halt within 16 micro-frames after software
clears the Run bit. The HC Halted bit in the status register indicates when the Host
Controller has finished its pending pipelined transactions and has entered the stopped
state.
Software must not write a one to this field unless the host controller is in the Halted
state (i.e. HCHalted in the USBSTS register is a one). Doing so will yield undefined
results.
USB Status (USBSTS)—Offset 14h
This register indicates pending interrupts and various states of the Host Controller. The
status resulting from a transaction on the serial bus is not indicated in this register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 14h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00001000h
August 2015
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Datasheet
555
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
usbint
0
usberrint
0
frame_list_rollover
0
0
port_change_detect
0
host_system_error
0
4
intr_on_async_advance
0
8
reserved_11_6
0
12
hchalted
0
16
reclamation
0
20
async_schedule_status
0
24
reserved_31_16
0
28
periodic_schedule_status
31
Field Name (ID): Description
0h
RO
reserved_31_16: Reserved bits.
These bits are reserved and should be set to zero.
0h
RO
Asynchronous Schedule Status (async_schedule_status): The bit reports the
current real status of the Asynchronous Schedule. If this bit is a zero then the status of
the Asynchronous Schedule is disabled. If this bit is a one then the status of the
Asynchronous Schedule is enabled.
The Host Controller is not required to immediately disable or enable the Asynchronous
Schedule when software transitions the Asynchronous Schedule Enable bit in the
USBCMD register. When this bit and the Asynchronous Schedule Enable bit are the same
value, the Asynchronous Schedule is either enabled (1) or disabled (0).
14
0h
RO
Periodic Schedule Status (periodic_schedule_status): The bit reports the current
real status of the Periodic Schedule. If this bit is a zero then the status of the Periodic
Schedule is disabled. If this bit is a one then the status of the Periodic Schedule is
enabled.
The Host Controller is not required to immediately disable or enable the Periodic
Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD
register. When this bit and the Periodic Schedule Enable bit are the same value, the
Periodic Schedule is either enabled (1) or disabled (0).
13
0h
RO
Reclamation (reclamation): This bit is used to detect an empty asynchronous
schedule.
12
1h
RO
HcHalted (hchalted): This bit is a zero whenever the Run/Stop bit is a one. The Host
Controller sets this bit to one after it has stopped executing as a result of the Run/Stop
bit being set to 0, either by software or by the Host Controller hardware (e.g. internal
error).
11:6
0h
RO
reserved_11_6: Reserved bits.
These bits are reserved and should be set to zero.
31:16
15
5
4
3
Intel® Quark™ SoC X1000
Datasheet
556
0h
RW/1C
Interrupt on Async Advance (intr_on_async_advance): System software can
force the host controller to issue an interrupt the next time the host controller advances
the asynchronous schedule by writing a one to the Interrupt on Async Advance Doorbell
bit in the USBCMD register. This status bit indicates the assertion of that interrupt
source.
0h
RW/1C
Host System Error (host_system_error): The Host Controller sets this bit to 1 when
a serious error occurs during a host system access involving the Host Controller module.
In a PCI system, conditions that set this bit to 1 include PCI Parity error, PCI Master
Abort, and PCI Target Abort.
When this error occurs, the Host Controller clears the Run/Stop bit in the Command
register to prevent further execution of the scheduled TDs.
0h
RW/1C
Frame List Rollover (frame_list_rollover): The Host Controller sets this bit to a one
when the Frame List Index rolls over from its maximum value to zero. The exact value
at which the rollover occurs depends on the frame list size. For example, if the frame list
size (as programmed in the Frame List Size field of the USBCMD register) is 1024, the
Frame Index Register rolls over every time FRINDEX[13] toggles. Similarly, if the size is
512, the Host Controller sets this bit to a one every time FRINDEX[12] toggles.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW/1C
Port Change Detect (port_change_detect): The Host Controller sets this bit to a
one when any port for which the Port Owner bit is set to zero has a change bit transition
from a zero to a one or a Force Port Resume bit transition from a zero to a one as a
result of a J-K transition detected on a suspended port. This bit will also be set as a
result of the Connect Status Change being set to a one after system software has
relinquished ownership of a connected port by writing a one to a port's Port Owner bit.
On a D3 to D0 transition of the EHCI HC device, this bit is loaded with the OR of all of
the PORTSC change bits (including: Force port resume, over-current change, enable/
disable change and connect status change).
1
0h
RW/1C
USB Error Interrupt (usberrint): The Host Controller sets this bit to 1 when
completion of a USB transaction results in an error condition (e.g., error counter
underflow). If the TD on which the error interrupt occurred also had its IOC bit set, both
this bit and USBINT bit are set.
Refer to EHCI Specification for a list of the USB errors that will result in this bit being set
to a one.
0
0h
RW/1C
USB Interrupt (usbint): The Host Controller sets this bit to 1 on the completion of a
USB transaction, which results in the retirement of a Transfer Descriptor that had its IOC
bit set. The Host Controller also sets this bit to 1 when a short packet is detected (actual
number of bytes received was less than the expected number of bytes).
2
16.6.2.6
USB Interrupt Enable (USBINTR)—Offset 18h
This register enables and disables reporting of the corresponding interrupt to the
software. When a bit is set and the corresponding interrupt is active, an interrupt is
generated to the host. Interrupt sources that are disabled in this register still appear in
the USBSTS to allow the software to poll for events.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 18h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
4
0
0
0
0
0
0
0
0
0
usbint_enable
0
8
usberrint_enable
0
12
port_change_intr_enable
0
16
host_system_err_enable
0
20
frame_list_rollover_enable
0
24
reserved_31_6
0
28
intr_on_async_advance_enable
31
Field Name (ID): Description
31:6
0h
RO
reserved_31_6: Reserved bits.
These bits are reserved and should be set to zero.
5
0h
RW
Interrupt on Async Advance Enable (intr_on_async_advance_enable): When
this bit is a one, and the Interrupt on Async Advance bit in the USBSTS register is a one,
the host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software clearing the Interrupt on Async Advance bit.
August 2015
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Intel® Quark™ SoC X1000
Datasheet
557
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.2.7
Default &
Access
Field Name (ID): Description
4
0h
RW
Host System Error Enable (host_system_err_enable): When this bit is a one, and
the Host System Error Status bit in the USBSTS register is a one, the host controller will
issue an interrupt. The interrupt is acknowledged by software clearing the Host System
Error bit.
3
0h
RW
Frame List Rollover Enable (frame_list_rollover_enable): When this bit is a one,
and the Frame List Rollover bit in the USBSTS register is a one, the host controller will
issue an interrupt. The interrupt is acknowledged by software clearing the Frame List
Rollover bit
2
0h
RW
Port Change Interrupt Enable (port_change_intr_enable): When this bit is a one,
and the Port Change Detect bit in the USBSTS register is a one, the host controller will
issue an interrupt. The interrupt is acknowledged by software clearing the Port Change
Detect bit.
1
0h
RW
USB Error Interrupt Enable (usberrint_enable): When this bit is a one, and the
USBERRINT bit in the USBSTS register is a one, the host controller will issue an interrupt
at the next interrupt threshold. The interrupt is acknowledged by software clearing the
USBERRINT bit.
0
0h
RW
USB Interrupt Enable (usbint_enable): When this bit is a one, and the USBINT bit in
the USBSTS register is a one, the host controller will issue an interrupt at the next
interrupt threshold. The interrupt is acknowledged by software clearing the USBINT bit.
USB Frame Index (FRINDEX)—Offset 1Ch
This register is used by the host controller to index into the periodic frame list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 1Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
31:14
Intel® Quark™ SoC X1000
Datasheet
558
Default &
Access
0h
RO
4
0
0
0
0
0
0
0
0
0
frame_index
reserved_31_14
0
Field Name (ID): Description
reserved_31_14: Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW
Frame Index (frame_index): The value of this register increments at the end of each
time frame (e.g. micro-frame). Bits [N:3] are used for the Frame List current index. This
means that each location of the frame list is accessed 8 times (frames or micro-frames)
before moving to the next index. The following illustrates values of N based on the value
of the Frame List Size field in the USBCMD register. USBCMD[Frame List Size] Number
Elements N
USBCMD[Frame List Size] = 00 (1024), N = 12
USBCMD[Frame List Size] = 01 (512), N = 11
USBCMD[Frame List Size] = 10 (256), N = 10
USBCMD[Frame List Size] = 11 (Reserved)
This register must be written as a DWord. Byte writes produce undefined results. This
register cannot be written unless the Host Controller is in the Halted state as indicated
by the HCHalted bit in USBSTS register. A write to this register while the Run/Stop bit of
USBCMD register is set to a one produces undefined results. Writes to this register also
affect the SOF value.
13:0
16.6.2.8
4 Gigabyte Memory Segment Selector (CTRLDSSEGMENT)—Offset 20h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 20h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
seg_4g_selector
0
28
Bit
Range
31:0
16.6.2.9
Default &
Access
Field Name (ID): Description
0h
RO
4 Gigabyte Memory Segment Selector (seg_4g_selector): This 32-bit register
corresponds to the most significant address bits [63:32] for all EHCI data structures.
If the 64-bit Addressing Capability field in HCCPARAMS is a zero, then this register is not
used. Software cannot write to it and a read from this register will return zeros.
If the 64-bit Addressing Capability field in HCCPARAMS is a one, then this register is
used with the link pointers to construct 64-bit addresses to EHCI control data
structures. This register allows the host software to locate all control data structures
within the same 4 Gigabyte memory segment.
NOTE: 64-bit Addressing is not supported
Periodic Frame List Base Address (PERIODICLISTBASE)—Offset 24h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 24h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
August 2015
Document Number: 329676-005US
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Datasheet
559
Intel® Quark™ SoC X1000—USB 2.0
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
Bit
Range
16.6.2.10
0
0
0
0
0
0
0
0
reserved_11_0
base_address
0
28
Default &
Access
Field Name (ID): Description
31:12
0h
RW
Base Address (base_address): This field contains bits [31:12]of the 32 bit address of
the Periodic Frame List in the system memory. System software loads this register prior
to starting the schedule execution by the Host Controller. The memory structure
referenced by this physical memory pointer is assumed to be 4-Kbyte aligned. The
contents of this register are combined with the Frame Index Register (FRINDEX) to
enable the Host Controller to step through the Periodic Frame List in sequence. Writes
must be DWord Writes.
11:0
0h
RO
reserved_11_0: Reserved bits.
Must be written as 0s. During runtime the value of these bits is undefined.
Asynchronous List Address (ASYNCLISTADDR)—Offset 28h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 28h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
lpl
0
28
Bit
Range
16.6.2.11
0
0
0
0
0
0
0
reserved_4_0
31
Default &
Access
Field Name (ID): Description
31:5
0h
RW
Link Pointer Low (lpl): This field contains bit [31:5] of the address of the next
asynchronous queue head to be executed. The memory structure referenced by this
physical memory pointer is assumed to be 4-Kbyte aligned. The contents of this register
are combined with the Frame Index Register (FRINDEX) to enable the Host Controller to
step through the Periodic Frame List in sequence. This field may only reference a Queue
Head (QH).
4:0
0h
RO
reserved_4_0: Reserved bits.
These bits are reserved and their value has no effect on operation.
Configure Flag (CONFIGFLAG)—Offset 50h
This register is in the auxiliary power well. It is only reset by hardware when the
auxiliary power is initially applied or in response to a host controller reset.
Access Method
Intel® Quark™ SoC X1000
Datasheet
560
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 50h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31:1
0
16.6.2.12
0
cf
reserved_31_1
0
28
Field Name (ID): Description
0h
RO
reserved_31_1: Reserved bits.
These bits are reserved and should be set to zero.
0h
RW
Configure Flag (cf): Host software sets this bit as the last action in its process of
configuring the Host Controller. This bit controls the default port-routing control logic.
Bit values and side-effects are listed below.
0: Port routing control logic default-routes each port to an implementation dependent
classic host controller.
1: Port routing control logic default-routes all ports to this host controller
Port Status/Control[0-1] (PORTSC[0-1])—Offset 54h, Count 2, Stride
4h
This register is in the auxiliary power well. It is only reset by hardware when the
auxiliary power is initially applied or in response to a host controller reset.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset[0-1]: [BAR0] + 54h + [0-1]*4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00002000h
Bit
Range
31:25
Default &
Access
0h
RO
August 2015
Document Number: 329676-005US
1
0
0
0
0
0
0
0
0
0
0
0
0
0
current_connect_status
0
port_enable_disable
0
connect_status_change
0
over_current_active
0
0
port_en_dis_change
0
over_current_change
0
suspend
0
force_port_resume
0
port_reset
0
4
suspend_using_l1
0
8
line_status
suspend_status
0
pp
0
port_owner
0
12
port_indicator_ctrl
0
16
port_test_ctrl
0
wkcnnt_e
0
20
wkoc_e
0
24
device_address
0
28
wkdscnnt_e
31
Field Name (ID): Description
Device Address (device_address): The 7-bit USB device address for the device
attached to and immediately downstream of the associated root port. A value of zero
indicates no device is present or support for this feature is not present.
NOTE: This field is not supported.
Intel® Quark™ SoC X1000
Datasheet
561
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
24:23
0h
RO
Suspend Status (suspend_status): These two bits are used by software to
determine whether the most recent L1 suspend request was successful.
NOTE: This field is not supported.
22
0h
RW
Wake on Over-current Enable (wkoc_e): Writing this bit to a one enables the port
to be sensitive to over-current conditions as wake-up events. This field is zero if Port
Power is zero.
21
0h
RW
Wake on Disconnect Enable (wkdscnnt_e): Writing this bit to a one enables the
port to be sensitive to device disconnects as wake-up events. This field is zero if Port
Power is zero.
20
0h
RW
Wake on Connect Enable (wkcnnt_e): Writing this bit to a one enables the port to
be sensitive to device connects as wake-up events. This field is zero if Port Power is
zero.
0h
RW
Port Test Control (port_test_ctrl): When this field is zero, the port is NOT operating
in a test mode. A non-zero value indicates that it is operating in test mode and the
specific test mode is indicated by the specific value. The encoding of the test mode bits
are (0110 - 1111 are reserved):
0000: Test mode not enabled
0001: Test J_STATE
0010: Test K_STATE
0011: Test SE0_NAK
0100: Test Packet
0101: Test FORCE_ENABLE
00h
RW
Port Indicator Control (port_indicator_ctrl): Writing to these bits has no effect if
the Port Indicator (P_INDICATOR) bit in the HCSPARAMS register is a zero.
If P_INDICATOR bit is a one, then the bit encodings are:
00: Port indicators are off
01: Amber
10: Green
11: Undefined
This field is zero if Port Power is zero.
NOTE: Port Indicator is not supported.
1h
RW
Port Owner (port_owner): This bit unconditionally goes to a 0 when the Configured
bit in the CONFIGFLAG register makes a 0b to 1b transition. This bit unconditionally
goes to 1 whenever the Configured bit is zero. System software uses this field to release
ownership of the port to a selected host controller (in the event that the attached device
is not a high-speed device). Software writes a one to this bit when the attached device
is not a high-speed device. A one in this bit means that a companion host controller
owns and controls the port.
0h
RW
Port Power (pp): The function of this bit depends on the value of the Port Power
Control (PPC) field in the HCSPARAMS register. The behavior is as follows:
If PPC=0, PP=1 and RO: Host controller does not have port power control switches.
Each port is hard-wired to power.
If PPC=0, PP=1 or 0 and R/W: Host controller has port power control switches. This bit
represents the current setting of the switch (0 = off, 1 = on). When power is not
available on port (i.e. PP equals a 0),the port is non-functional and will not report
attaches, detaches, etc.
When an over-current condition is detected on a powered port and PPC is a one, the PP
bit in each affected port may be transitioned by the host controller from a 1 to 0
(removing power from the port).
NOTE: Per Port Power control is supported (PPC=1)
11:10
0h
RO
Line Status (line_status): These bits reflect the current logical levels of the D+ (bit
11) and D- (bit 10) signal lines. These bits are used for detection of low-speed USB
devices prior to the port reset and enable sequence. This field is valid only when the port
enable bit is zero and the current connect status bit is set to a one. The encoding of the
bits are:
Bits[11:10] USB State Interpretation
00: USB State is SE0, Not Low-speed device, perform EHCI reset
10: USB State is J-state, Not Low-speed device, perform EHCI reset
01: USB State is K-state, Low-speed device, release ownership of port
11: USB State is Undefined, Not Low-speed device, perform EHCI reset
The value of this field is undefined if Port Power is zero.
9
0h
RO
Suspend using l1 (suspend_using_l1): NOTE: suspend using l1 is not supported as
part of LPM.
19:16
15:14
13
12
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW
Port Reset (port_reset): 1: Port is in Reset
0: Port is not in Reset
When software writes a one to this bit (from a zero), the bus reset sequence as defined
in the USB Specification Revision 2.0 is started. Software writes a zero to this bit to
terminate the bus reset sequence. Software must keep this bit at a one long enough to
ensure the reset sequence, as specified in the USB Specification Revision 2.0,
completes.
When software writes this bit to a one, it must also write a zero to the Port Enable bit.
Note that when software writes a zero to this bit there may be a delay before the bit
status changes to a zero. The bit status will not read as a zero until after the reset has
completed. If the port is in high-speed mode after reset is complete, the host controller
will automatically enable this port (e.g. set the Port Enable bit to a one). A host
controller must terminate the reset and stabilize the state of the port within 2ms of
software transitioning this bit from a one to a zero. For example: if the port detects that
the attached device is high-speed during reset, then the host controller must have the
port in the enabled state within 2ms of software writing this bit to a zero.
The HCHalted bit in the USBSTS register should be a zero before software attempts to
use this bit. The host controller may hold Port Reset asserted to a one when the
HCHalted bit is a one. This field is zero if Port Power is zero.
0h
RW
Suspend (suspend): 1: Port in suspend state
0: Port not in suspend state
Port Enabled Bit and Suspend bit of this register define the port states as follows:
Bit [Port Enabled, Suspend]: Port State
0X: Disable
10: Enable
11: Suspend
When in suspend state, downstream propagation of data is blocked on this port, except
for port reset. The blocking occurs at the end of the current transaction, if a transaction
was in progress when this bit was written to 1. In the suspend state, the port is
sensitive to resume detection. Note that the bit status does not change until the port is
suspended and that there may be a delay in suspending a port if there is a transaction
currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The host controller will
unconditionally set this bit to a zero when:
Software sets the Force Port Resume bit to a zero (from a one).
Software sets the Port Reset bit to a one (from a zero).
If host software sets this bit to a one when the port is not enabled (i.e. Port enabled bit
is a zero) the results are undefined. This field is zero if Port Power is zero.
6
0h
RW
Force Port Resume (force_port_resume): 1: Resume detected/driven on port
0: No resume (K-state) detected/driven on port
This functionality defined for manipulating this bit depends on the value of the Suspend
bit.
For example, if the port is not suspended (Suspend and Enabled bits are a one) and
software transitions this bit to a one, then the effects on the bus are undefined.
Software sets this bit to a 1 to drive resume signaling. The Host Controller sets this bit
to a 1 if a J-to-K transition is detected while the port is in the Suspend state. When this
bit transitions to a one because a J-to-K transition is detected, the Port Change Detect
bit in the USBSTS register is also set to a one. If software sets this bit to a one, the host
controller must not set the Port Change Detect bit. Note that when the EHCI controller
owns the port, the resume sequence follows the defined sequence documented in the
USB Specification Revision 2.0. The resume signaling (Full-speed 'K') is driven on the
port as long as this bit remains a one. Software must appropriately time the Resume
and set this bit to a zero when the appropriate amount of time has elapsed. Writing a
zero (from one) causes the port to return to high-speed mode (forcing the bus below
the port into a high-speed idle). This bit will remain a one until the port has switched to
the high-speed idle. The host controller must complete this transition within 2
milliseconds of software setting this bit to a zero. This field is zero if Port Power is zero.
5
0h
RW/1C
Over Current Change (over_current_change): This bit gets set to a one when there
is a change to Over-current Active. Software clears this bit by writing a one to this bit
position.
4
0h
RO
8
7
August 2015
Document Number: 329676-005US
Over Current Active (over_current_active): 1: This port currently has an overcurrent condition
0: This port does not have an over-current condition
This bit will automatically transition from a one to a zero when the over current
condition is removed.
Intel® Quark™ SoC X1000
Datasheet
563
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
Field Name (ID): Description
0h
RW/1C
Port Enable/Disable Change (port_en_dis_change): 1: Port enabled/disabled
status has changed
0: No change
For the root hub, this bit gets set to a one only when a port is disabled due to the
appropriate conditions existing at the EOF2 point Software clears this bit by writing a 1
to it. This field is zero if Port Power is zero.
0h
RW
Port Enable/Disable (port_enable_disable): 1: Enable
0: Disable
Ports can only be enabled by the host controller as a part of the reset and enable.
Software cannot enable a port by writing a one to this field. The host controller will only
set this bit to a one when the reset sequence determines that the attached device is a
high-speed device. Ports can be disabled by either a fault condition (disconnect event or
other fault condition) or by host software. Note that the bit status does not change until
the port state actually changes. There may be a delay in disabling or enabling a port due
to other host controller and bus events. When the port is disabled (0) downstream
propagation of data is blocked on this port, except for reset. This field is zero if Port
Power is zero.
1
0h
RW/1C
Connect Status Change (connect_status_change): 1: Change in Current Connect
Status
0: No change
Indicates a change has occurred in the ports Current Connect Status. The host controller
sets this bit for all changes to the port device connect status, even if system software
has not cleared an existing connect status change. For example, the insertion status
changes twice before system software has cleared the changed condition, hub hardware
will be setting an already set bit. Software sets this bit to 0 by writing a 1 to it.
This field is zero if Port Power is zero.
0
0h
RO
Current Connect Status (current_connect_status): 1: Device is present on port
0: No device is present
This value reflects the current state of the port, and may not correspond directly to the
event that caused the Connect Status Change bit (Bit 1) to be set.
This field is zero if Port Power is zero.
3
2
16.6.2.13
Programmable Microframe Base Value (INSNREG00)—Offset 90h
This register allows changing the microframe length value (default is microframe SOF =
125ms) to reduce the simulation time.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 90h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
Bit
Range
31:14
Intel® Quark™ SoC X1000
Datasheet
564
Default &
Access
00000h
RO
4
0
uframe_count
reserved_31_14
0
0
0
0
0
0
0
0
0
uframe_count_en
31
Field Name (ID): Description
reserved_31_14: Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.2.14
Default &
Access
Field Name (ID): Description
13:1
0h
RW
uframe_count: 1-microframe counter with byte interface (8-bits).
0
0b
RW
uframe_count_en: 1-microframe counter is enabled when this bit is set to 1.
Programmable Packet Buffer OUT/IN Thresholds (INSNREG01)—
Offset 94h
This register allows setting the packet buffer OUT/IN thresholds. The value specified by
the thresholds is in number of DWORDs (32-bit entries). The minimum threshold
amount that can be programmed is the highest possible INCRX burst value (INCR16)
i.e the minimum OUT and IN threshold value should be 64 bytes (16 DWords). With the
implemented packet buffer depth of 512 bytes, OUT and IN threshold values can be
equal to the packet buffer depth only when isochronous/interrupt transactions are not
initiated by the host controller.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 94h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00200020h
0
0
0
0
0
Bit
Range
16.6.2.15
0
0
1
0
OUT_Threshold
0
20
Default &
Access
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
1
0
0
0
0
0
0
IN_Threshold
0
24
reserved_31_24
0
28
reserved_15_8
31
Field Name (ID): Description
31:24
00h
RO
reserved_31_24: Reserved bits.
These bits are reserved and should be set to zero.
23:16
20h
RW
Out Threshold (OUT_Threshold): The OUT threshold is used to start the USB transfer
as soon as the OUT threshold amount of data is fetched from system memory. It is also
used to disconnect the data fetch, if the threshold amount of space is not available in
the Packet Buffer.
15:8
00h
RO
reserved_15_8: Reserved bits.
These bits are reserved and should be set to zero.
7:0
20h
RW
IN Threshold (IN_Threshold): The IN threshold is used to start the memory transfer
as soon as the IN threshold amount of data is available in the Packet Buffer. It is also
used to disconnect the data write, if the threshold amount of data is not available in the
Packet Buffer.
Programmable Packet Buffer Depth (INSNREG02)—Offset 98h
Access Method
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
565
Intel® Quark™ SoC X1000—USB 2.0
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 98h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000080h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
Bit
Range
16.6.2.16
0
0
0
0
0
0
0
0
pkt_buffer_depth
reserved_31_12
0
28
Default &
Access
Field Name (ID): Description
31:12
0h
RO
reserved_31_12: Reserved bits.
These bits are reserved and should be set to zero.
11:0
80h
RW
Programmable Packet Buffer Depth (pkt_buffer_depth): The value specified here
is the number of DWORDs (32-bit entries).
Programmable Controller Settings (INSNREG03)—Offset 9Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + 9Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00002001h
0
0
0
0
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
1
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
Break_Memory
0
12
Time_available_offset
0
16
Periodic_Frame_List
0
20
Tx_Tx_turnaround_dly
0
24
reserved_31_14
0
28
TestSE0
31
Field Name (ID): Description
31:14
0h
RO
reserved_31_14: Reserved bits.
These bits are reserved and should be set to zero.
13
1h
RW
TestSE0 NAK (TestSE0): When set to 1 (default), the core ignores the line state
checking when transmitting SOF during the SE0_NAK test mode. When Set to 0, the
port state machine disables the port if it does not find the line state to be in SE0 when
transmitting SOF during the SE0_NAK testing. While doing impedance measurement
during the SE0_NAK testing, the line state could go to non SE0 forcing the core to
disable the port. This bit is used to control the port behavior during this.
Intel® Quark™ SoC X1000
Datasheet
566
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.2.17
Default &
Access
Field Name (ID): Description
12:10
0h
RW
Transmit to Transmit turnaround delay (Tx_Tx_turnaround_dly): This field
specifies the extra delays in phy_clks to be added to the Transmit to Transmit
turnaround delay value maintained in the core. The default value of this register field is
0. This default value of 0 is sufficient for most PHYs. But for some PHYs which puts wait
states during the token packet, it may be required to program a value greater than 0 to
meet the transmit to transmit minimum turnaround time. The recommendation to use
the default value of 0 and change it only if there is an issue with minimum transmit-totransmit turnaround time. This value should be programmed during core initialization
and should not be changed afterwards.
9
0h
RW
Periodic Frame List Fetch (Periodic_Frame_List): Setting this bit will force the host
controller to fetch the periodic frame list in every microframe of a frame. If not set, then
the periodic frame list will be fetched only in microframe 0 of every frame. The default is
0 (not set). This bit can be changed only during core initialization and should not be
changed afterwards.
8:1
0h
RW
Time Available Offset (Time_available_offset): This value indicates the additional
number of bytes to be accommodated for the time-available calculation. The USB traffic
on the bus can be started only when sufficient time is available to complete the packet
within the EOF1 point. This time-available calculation is done in the hardware, and can
be further offset by programming a value in this location. Note that time-available
calculation is added for future flexibility and the application is not required to program
this field by default.
0
1h
RO
Break Memory Transfer (Break_Memory): 1: Enables this function
0: Disables this function
Used in conjunction with INSNREG01 to enable breaking memory transactions into
chunks once the OUT/IN threshold value is reached.
Programmable Controller Settings (INSNREG04)—Offset A0h
Bits [2:0] are used only for debug purposes.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + A0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0
0
0
0
Bit
Range
31:6
Default &
Access
0h
RO
August 2015
Document Number: 329676-005US
4
0
0
0
0
0
0
0
0
0
sys_res
0
12
port_enum
0
16
NAK
0
20
reserved_3
0
24
reserved_31_6
0
28
automatic_feature
31
Field Name (ID): Description
reserved_31_6: Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
567
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.2.18
Default &
Access
Field Name (ID): Description
5
0h
RW
Automatic Suspend Feature (automatic_feature): 0: enables the automatic
feature. The Suspend signal is deasserted (logic level 1) when run/stop is reset by
software, but the hchalted bit is not yet set.
1: disables the automatic feature, which takes all ports out of suspend when software
clears the run/stop bit. This is for backward compatibility.
For systems where the host is halted without waking up all ports out of suspend, the
port can become stuck because the PHYCLK is not running when the halt is
programmed. To avoid this, the DWC H20AHB host core automatically pulls ports out of
suspend when the host is halted by software. This bit is used to disable this automatic
function.
This is a functional bit.
4
0h
RW
NAK reload fix enabled (NAK): When 1 NAK reload fix disabled.
This is a functional bit for backward compatibility with Synopsys USB 2.0 Host-AHB core
Release 2.40c.
3
0h
RO
reserved_3: Reserved bits.
These bits are reserved and should be set to zero.
2
0h
RW
Port Enumeration Time (port_enum): Scales down port enumeration time. This is a
debug bit.
1:0
0h
RW
System Reset (sys_res): When sys_res[1]=1, HCCPARAMS bits 17,15:4 become
writable.
When sys_res[0]=1, HCCPARAMS register become writable Upon system reset, this field
is 0. This is a debug bit.
UTMI Configuration (INSNREG05)—Offset A4h
This register gives access to implementation specific PHY vendor control and status
registers. NOTE: Vendor control and status registers are not implemented. Read from
Vendor Status will always return 0. Write to Vendor Control will have no effect.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
Offset: [BAR0] + A4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:3] + 10h
Default: 00001000h
0
0
0
Bit
Range
31:18
17
Intel® Quark™ SoC X1000
Datasheet
568
Default &
Access
0h
RO
0h
RO/V
20
0
0
0
0
16
0
0
0
0
12
0
0
0
1
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
Vstatus
24
0
Vcontrol
0
VControlLoadM
0
Vport
28
0
reserved_31_18
0
Vbusy
31
Field Name (ID): Description
reserved_31_18: Reserved bits.
These bits are reserved and should be set to zero.
Vbusy: Hardware indicator that a write to this register has occurred and the hardware is
currently processing the operation defined by the data written. When processing is
finished, this bit is cleared.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Field Name (ID): Description
16:13
0h
RW
Vport: Port number from/to the PHY Vendor Status and Control value is read/written in
Vstatus field.
Vport meaningful values depend on the number of ports implemented. Allowed values
are 4'h1 and 4'h2, any other value will return Vstatus=8'h0.
Once software writes to VPort, from that write onwards, any writes to this register is
ignored.
12
1h
RW
Vendor Control Load (VControlLoadM): 0: Load.
1: NOP.
11:8
0h
RW
Vendor control register (Vcontrol): Not implemented - write to Vendor Control will
have no effect.
7:0
0h
RO
Vendor Status register (Vstatus): Not implemented - read from Vendor Status will
always return 0.
16.6.3
USB OHCI
Table 108.
Summary of Memory Mapped I/O Registers—BAR0
Offset Start
Offset End
Default
Value
Register ID—Description
0h
3h
“OHCI Revision (HCREVISION)—Offset 0h” on page 570
00000010h
4h
7h
“Host Controller Control (HCCONTROL)—Offset 4h” on page 570
00000000h
8h
Bh
“Host Controller Command Status (HCCMDSTATUS)—Offset 8h” on page 571
00000000h
Ch
Fh
“Host Controller Interrupt Status (HCINTRSTATUS)—Offset Ch” on page 573
00000000h
10h
13h
“Host Controller Interrupt Enable (HCINTRENABLE)—Offset 10h” on page 574
00000000h
14h
17h
“Host Controller Interrupt Disable (HCINTRDISABLE)—Offset 14h” on page 575
00000000h
18h
1Bh
“Host Controller Communication Area (HCHCCA)—Offset 18h” on page 576
00000000h
1Ch
1Fh
“Host Controller Current Isochronous or Interrupt Endpoint (HCPRDCURED)—
Offset 1Ch” on page 577
00000000h
20h
23h
“Host Controller Current First Control Endpoint (HCCTRLHEADED)—Offset 20h” on
00000000h
page 577
24h
27h
“Host Controller Current Control Endpoint (HCCTRLCURED)—Offset 24h” on
page 578
00000000h
28h
2Bh
“Host Controller First Bulk Endpoint (HCBULKHEADED)—Offset 28h” on page 578
00000000h
2Ch
2Fh
“Host Controller Current Bulk Endpoint (HCBULKCURED)—Offset 2Ch” on page 579 00000000h
30h
33h
“Host Controller Last Completed Descriptor (HCDONEHEAD)—Offset 30h” on
page 580
00000000h
34h
37h
“Host Controller Frame Interval (HCFMINTERVAL)—Offset 34h” on page 580
00002EDFh
38h
3Bh
“Host Controller Remaining Frame (HCFMREMAINING)—Offset 38h” on page 581
00000000h
3Ch
3Fh
“Host Controller Frame Number (HCFMNUMBER)—Offset 3Ch” on page 582
00000000h
40h
43h
“Host Controller Periodic List Start (HCPERIODICSTART)—Offset 40h” on page 583 00000000h
44h
47h
“Host Controller LS Threshold (HCLSTHRESHOLD)—Offset 44h” on page 583
00000628h
48h
4Bh
“Host Controller Root Hub Descriptor A (HCRHDESPA)—Offset 48h” on page 584
02000902h
4Ch
4Fh
“Host Controller Root Hub Descriptor B (HCRHDESPB)—Offset 4Ch” on page 585
00000000h
50h
53h
“Host Controller Root Hub Status (HCRHSTATUS)—Offset 50h” on page 586
00000000h
54h
57h
“Host Controller Root Hub Port Status (HCRHPORTSTS)—Offset 54h” on page 587
00000000h
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
569
Intel® Quark™ SoC X1000—USB 2.0
16.6.3.1
OHCI Revision (HCREVISION)—Offset 0h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCREVISION: [BAR0] + 0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000010h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
Bit
Range
Default &
Access
000000h
RO
31: 8
16.6.3.2
1
0
0
0
0
Description
reserved_31_8 (reserved_31_8): Reserved bits.
These bits are reserved and should be set to zero.
10h
RO
7: 0
0
revision
reserved_31_8
0
28
Revision (revision): This read-only field contains the BCD representation of the
version of the HCI specification that is implemented by this HC.
Host Controller Control (HCCONTROL)—Offset 4h
The HCCONTROL register defines the operating modes for the Host Controller (HC).
Most of the fields in this register are modified only by the Host Controller Driver (HCD),
except hc_function_state and rmtwkup_connected.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCCONTROL: [BAR0] + 4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
Bit
Range
Default &
Access
31: 11
0h
RO
Intel® Quark™ SoC X1000
Datasheet
570
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ctrlbulk_serviceratio
0
periodiclist_enable
0
0
isoc_enable
0
4
ctrllist_enable
0
8
bulklist_enable
0
12
hc_function_state
0
16
intr_routing
0
20
rmtwkup_enable
0
24
reserved_31_11
0
28
rmtwkup_connected
31
Description
reserved_31_11 (reserved_31_11): Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
10
0h
RW
Remote Wakeup Enable (rmtwkup_enable): This bit is used by HCD to enable or
disable the remote wakeup feature upon the detection of upstream resume signaling.
When this bit is set and the resume_detected bit in HCINTRSTATUS is set, a remote
wakeup is signaled to the host system. Setting this bit has no impact on the generation
of hardware interrupts.
9
0h
RW
Remote Wakeup Connected (rmtwkup_connected): This bit indicates whether HC
supports remote wakeup signaling. If remote wakeup is supported and used by the
system it is the responsibility of system firmware to set this bit during POST. HC clears
the bit upon a hardware reset but does not alter it upon a software reset.
8
0h
RW
Interrupt Routing (intr_routing): This bit determines the routing of interrupts
generated by events registered in HCINTRSTATUS. If clear, all interrupts are routed to
the normal host bus interrupt mechanism. If set, interrupts are routed to the System
Management Interrupt. HCD clears this bit upon a hardware reset, but it does not alter
this bit upon a software reset. HCD uses this bit as a tag to indicate the ownership of
HC.
7: 6
0h
RW
Host Controller Functional State for USB (hc_function_state): 00: USBRESET
01: USBRESUME
10: USBOPERATIONAL
11: USBSUSPEND
A transition to USBOPERATIONAL from another state causes SOF generation to begin
1ms later. HCD may determine whether HC has begun sending SOFs by reading the
start_of_frame field of HCINTRSTATUS. This field may be changed by HC only when in
the USBSUSPEND state. HC may move from the USBSUSPEND state to the USBRESUME
state after detecting the resume signaling from a downstream port. HC enters
USBSUSPEND after software reset, whereas it enters USBRESET after a hardware reset.
The latter also resets the Root Hub and asserts subsequent reset signaling to
downstream ports.
5
0h
RW
Bulk List Enable (bulklist_enable): This bit is set to enable the processing of the
Bulk list in the next Frame. If cleared by HCD, processing of the Bulk list does not occur
after the next SOF. HC checks this bit whenever it determines to process the list. When
disabled, HCD may modify the list. If HCBULKCURED is pointing to an ED (Endpoint
Descriptor) to be removed, HCD must advance the pointer by updating HCBULKCURED
before re-enabling processing of the list.
0h
RW
Control List Enable (ctrllist_enable): This bit is set to enable the processing of the
Control list in the next Frame. If cleared by HCD, processing of the Control list does not
occur after the next SOF. HC must check this bit whenever it determines to process the
list. When disabled, HCD may modify the list. If HCCTRLCURED is pointing to an ED to
be removed, HCD must advance the pointer by updating HCCTRLCURED before reenabling processing of the list.
3
0h
RW
Isochronous Enable (isoc_enable): This bit is used by HCD to enable/disable
processing of isochronous ED's. While processing the periodic list in a Frame, HC checks
the status of this bit when it finds an Isochronous ED (F=1). If set (enabled), HC
continues processing the ED's. If cleared (disabled), HC halts processing of the periodic
list (which now contains only isochronous ED's) and begins processing the Bulk/Control
lists. Setting this bit is guaranteed to take effect in the next Frame (not the current
Frame).
2
0h
RW
Periodic List Enable (periodiclist_enable): This bit is set to enable the processing of
the periodic list in the next Frame. If cleared by HCD, processing of the periodic list does
not occur after the next SOF. HC must check this bit before it starts processing the list.
1: 0
0h
RW
Control Bulk Service Ratio (ctrlbulk_serviceratio): This specifies the service ratio
between Control and Bulk ED's. Before processing any of the nonperiodic lists, HC must
compare the ratio specified with its internal count on how many nonempty Control ED's
have been processed, in determining whether to continue serving another Control ED or
switching to Bulk ED's. The internal count will be retained when crossing the frame
boundary. In case of reset, HCD is responsible for restoring this value.
4
16.6.3.3
Host Controller Command Status (HCCMDSTATUS)—Offset 8h
The HCCMDSTATUS register is used by the Host Controller to receive commands issued
by the Host Controller Driver, as well as reflecting the current status of the Host
Controller. To the Host Controller Driver, it appears to be a 'write to set' register. The
Host Controller must ensure that bits written as 1 become set in the register while bits
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
571
Intel® Quark™ SoC X1000—USB 2.0
written as 0 remain unchanged in the register. The Host Controller Driver may issue
multiple distinct commands to the Host Controller without concern for corrupting
previously issued commands. The Host Controller Driver has normal read access to all
bits. The sch_overrun_cnt field indicates the number of frames with which the Host
Controller has detected the scheduling overrun error. This occurs when the Periodic list
does not complete before EOF. When a scheduling overrun error is detected, the Host
Controller increments the counter and sets the sch_overrun field in the HCINTRSTATUS
register.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCCMDSTATUS: [BAR0] + 8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
hcreset
0
8
ctrllist_filled
0
12
bulklist_filled
0
16
ownerchange_req
0
20
reserved_15_4
0
24
reserved_31_18
0
28
sch_overrun_cnt
31
Bit
Range
Default &
Access
31: 18
0h
RO
reserved_31_18 (reserved_31_18): Reserved bits.
These bits are reserved and should be set to zero.
17: 16
0h
RO
Scheduling Overrun Count (sch_overrun_cnt): These bits are incremented on each
scheduling overrun error. It is initialized to 00b and wraps around at 11b. This will be
incremented when a scheduling overrun is detected even if sch_overrun in
HCINTRSTATUS has already been set. This is used by HCD to monitor any persistent
scheduling problems
15: 4
0h
RO
reserved_15_4 (reserved_15_4): Reserved bits.
These bits are reserved and should be set to zero.
3
0h
RW/1C
Ownership Change Request (ownerchange_req): This bit is set by an OS HCD to
request a change of control of the HC. When set HC will set the ownerchange_req field
in HCINTRSTATUS. After the changeover, this bit is cleared and remains so until the next
request from OS HCD.
0h
RW
BulkListFilled (bulklist_filled): This bit is used to indicate whether there are any TDs
on the Bulk list. It is set by HCD whenever it adds a TD to an ED in the Bulk list. When
HC begins to process the head of the Bulk list, it checks bulklist_filled. As long as
bulklist_filled is 0, HC will not start processing the Bulk list. If bulklist_filled is 1, HC will
start processing the Bulk list and will set bulklist_filled to 0. If HC finds a TD on the list,
then HC will set bulklist_filled to 1 causing the Bulk list processing to continue. If no TD
is found on the Bulk list, and if HCD does not set bulklist_filled, then bulklist_filled will
still be 0 when HC completes processing the Bulk list and Bulk list processing will stop.
0h
RW
Control List Filled (ctrllist_filled): This bit is used to indicate whether there are any
TDs on the Control list. It is set by HCD whenever it adds a TD to an ED in the Control
list. When HC begins to process the head of the Control list, it checks ctrllist_filled. As
long as ctrllist_filled is 0, HC will not start processing the Control list. If CF is 1, HC will
start processing the Control list and will set ctrllist_filled to 0. If HC finds a TD on the
list, then HC will set ctrllist_filled to 1 causing the Control list processing to continue. If
no TD is found on the Control list, and if the HCD does not set ctrllist_filled, then
ctrllist_filled will still be 0 when HC completes processing the Control list and Control list
processing will stop.
2
1
Intel® Quark™ SoC X1000
Datasheet
572
Description
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
0h
RW
Host Controller Reset (hcreset): This bit is set by HCD to initiate a software reset of
HC. Regardless of the functional state of HC, it moves to the USBSUSPEND state in
which most of the operational registers are reset except those stated otherwise; e.g.,
the intr_routing field of HCCONTROL, and no Host bus accesses are allowed. This bit is
cleared by HC upon the completion of the reset operation. The reset operation must be
completed within 10ms. This bit, when set, should not cause a reset to the Root Hub
and no subsequent reset signaling should be asserted to its downstream ports.
0
16.6.3.4
Host Controller Interrupt Status (HCINTRSTATUS)—Offset Ch
This register provides status on various events that cause hardware interrupts. When
an event occurs, Host Controller sets the corresponding bit in this register. When a bit
becomes set, a hardware interrupt is generated if the interrupt is enabled in the
HCINTRENABLE register and the mstr_intr_enable bit is set. The Host Controller Driver
may clear specific bits in this register by writing 1 to bit positions to be cleared. The
Host Controller Driver may not set any of these bits. The Host Controller will never
clear the bit.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCINTRSTATUS: [BAR0] + Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
Bit
Range
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
Default &
Access
0
4
0
0
0
0
0
0
0
0
0
sch_overrun
0
start_of_frame
0
wrback_donehead
0
unrecov_err
24
0
resume_detected
0
reserved_29_07
reserved_31
0
rhub_stschange
28
0
owner_change
0
fmnum_overflow
31
Description
31
0h
RO
30
0h
RW/1C
29: 7
0h
RO
6
0h
RW/1C
Root Hub Status Change (rhub_stschange): This bit is set when the content of
HCRHSTATUS or the content of any of HCRHPORTSTS[NumberofDownstreamPort] has
changed.
5
0h
RW/1C
Frame Number Overflow (fmnum_overflow): This bit is set when the MSb of
HCFMNUMBER (bit 15) changes value, from 0 to 1 or from 1 to 0, and after
HccaFrameNumber has been updated.
4
0h
RW/1C
Unrecoverable Error (unrecov_err): This bit is set when HC detects a system error
not related to USB. HC should not proceed with any processing or signaling before the
system error has been corrected. HCD clears this bit after HC has been reset.
August 2015
Document Number: 329676-005US
reserved_31 (reserved_31): Reserved bits.
These bits are reserved and should be set to zero.
Ownership Change (owner_change): This bit is set by HC when HCD sets the
ownerchange_req field in HCCMDSTATUS. This event, when unmasked, will always
generate a System Management Interrupt (SMI) immediately. This bit is tied to 0 when
the SMI pin is not implemented.
NOTE: OHCI SMIs are ignored by the system.
reserved_29_07 (reserved_29_07): Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
573
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.3.5
Default &
Access
Description
3
0h
RW/1C
Resume Detected (resume_detected): This bit is set when HC detects that a device
on the USB is asserting resume signaling. It is the transition from no resume signaling
to resume signaling causing this bit to be set. This bit is not set when HCD sets the
USBRESUME state.
2
0h
RW/1C
Start of Frame (start_of_frame): This bit is set by HC at each start of a frame and
after the update of HccaFrameNumber. HC also generates a SOF token at the same
time.
1
0h
RW/1C
Writeback Done Head (wrback_donehead): This bit is set immediately after HC has
written HCDONEHEAD to HccaDoneHead. Further updates of the HccaDoneHead will not
occur until this bit has been cleared. HCD should only clear this bit after it has saved the
content of HccaDoneHead.
0
0h
RW/1C
Scheduling Overrun (sch_overrun): This bit is set when the USB schedule for the
current Frame overruns and after the update of HccaFrameNumber. A scheduling
overrun will also cause the sch_overrun_cnt of HCCMDSTATUS to be incremented.
Host Controller Interrupt Enable (HCINTRENABLE)—Offset 10h
Each enable bit in the HCINTRENABLE register corresponds to an associated interrupt
bit in the HCINTRSTATUS register. The HCINTRENABLE register is used to control which
events generate a hardware interrupt. When a bit is set in the HCINTRSTATUS register
AND the corresponding bit in the HCINTRENABLE register is set AND the
mstr_intr_enable bit is set, then a hardware interrupt is requested on the host bus.
Writing a '1' to a bit in this register sets the corresponding bit, whereas writing a '0' to
a bit in this register leaves the corresponding bit unchanged. On read, the current value
of this register is returned.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCINTRENABLE: [BAR0] + 10h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
Bit
Range
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
sch_overrun_enb
0
wrback_donehead_enb
0
start_of_frame_enb
0
unrecov_err_enb
24
0
resume_detected_enb
0
rhub_stschange_enb
mstr_intr_enable
0
fmnum_overflow_enb
28
0
owner_change_enb
0
reserved_29_07
31
Default &
Access
Description
31
0h
RW/1S
Master Interrupt Enable (mstr_intr_enable): A 0 written to this field is ignored by
HC. A 1 written to this field enables interrupt generation due to events specified in the
other bits of this register. This is used by HCD as a Master Interrupt Enable.
30
0h
RW/1S
Owner Change Enable (owner_change_enb): 0: Ignore
1: Enable interrupt generation due to Ownership Change.
29: 7
0h
RO
Intel® Quark™ SoC X1000
Datasheet
574
reserved_29_07 (reserved_29_07): Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
Bit
Range
16.6.3.6
Default &
Access
Description
6
0h
RW/1S
Root Hub Status Change Enable (rhub_stschange_enb): 0: Ignore
1: Enable interrupt generation due to Root Hub Status Change
5
0h
RW/1S
Frame Number Overflow Enable (fmnum_overflow_enb): 0: Ignore
1: Enable interrupt generation due to Frame Number Overflow
4
0h
RW/1S
Unrecoverable Error Enable (unrecov_err_enb): 0: Ignore
1: Enable interrupt generation due to Unrecoverable Error
3
0h
RW/1S
Resume Detected Enable (resume_detected_enb): 0: Ignore
1: Enable interrupt generation due to Resume Detect
2
0h
RW/1S
Start of Frame Enable (start_of_frame_enb): 0: Ignore
1: Enable interrupt generation due to Start of Frame
1
0h
RW/1S
HCDONEHEAD Writeback Enable (wrback_donehead_enb): 0: Ignore
1: Enable interrupt generation due to HCDONEHEAD Writeback
0
0h
RW/1S
Scheduling Overrun Enable (sch_overrun_enb): 0: Ignore
1: Enable interrupt generation due to Scheduling Overrun
Host Controller Interrupt Disable (HCINTRDISABLE)—Offset 14h
Each disable bit in the HCINTRDISABLE register corresponds to an associated interrupt
bit in the HCINTRSTATUS register. The HCINTRDISABLE register is coupled with the
HCINTRENABLE register. Thus, writing a '1' to a bit in this register clears the
corresponding bit in the HCINTRENABLE register, whereas writing a '0' to a bit in this
register leaves the corresponding bit in the HCINTRENABLE register unchanged. On
read, the current value of the HCINTRENABLE register is returned.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCINTRDISABLE: [BAR0] + 14h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
Bit
Range
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
sch_overrun_dbl
0
start_of_frame_dbl
0
wrback_donehead_dbl
0
unrecov_err_dbl
24
0
resume_detected_dbl
0
reserved_29_07
mstr_intr_enable
0
rhub_stschange_dbl
28
0
owner_change_dbl
0
fmnum_overflow_dbl
31
Default &
Access
Description
31
0h
RW/1C
Master Interrupt Enable (mstr_intr_enable): A '0' written to this field is ignored by
HC. A '1' written to this field disables interrupt generation due to events specified in the
other bits of this register. This field is set after a hardware or software reset.
30
0h
RW/1C
Owner Change Disable (owner_change_dbl): 0: Ignore
1: Disable interrupt generation due to Ownership Change
29: 7
0h
RO
August 2015
Document Number: 329676-005US
reserved_29_07 (reserved_29_07): Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
575
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.3.7
Default &
Access
Description
6
0h
RW/1C
Root Hub Status Change Disable (rhub_stschange_dbl): 0: Ignore
1: Disable interrupt generation due to Root Hub Status Change
5
0h
RW/1C
Frame Number Overflow Disable (fmnum_overflow_dbl): 0: Ignore
1: Disable interrupt generation due to Frame Number Overflow
4
0h
RW/1C
Unrecoverable Error Disable (unrecov_err_dbl): 0: Ignore
1: Disable interrupt generation due to Unrecoverable Error
3
0h
RW/1C
Resume Detected Disable (resume_detected_dbl): 0: Ignore
1: Disable interrupt generation due to Resume Detect
2
0h
RW/1C
Start of Frame Disable (start_of_frame_dbl): 0: Ignore
1: Disable interrupt generation due to Start of Frame
1
0h
RW/1C
HCDONEHEAD Writeback Disable (wrback_donehead_dbl): 0: Ignore
1: Disable interrupt generation due to HCDONEHEAD Writeback
0
0h
RW/1C
Scheduling Overrun Disable (sch_overrun_dbl): 0: Ignore
1: Disable interrupt generation due to Scheduling Overrun
Host Controller Communication Area (HCHCCA)—Offset 18h
The HCHCCA register contains the physical address of the Host Controller
Communication Area. The Host Controller Driver determines the alignment restrictions
by writing all 1s to HCHCCA and reading the content of HCHCCA. The alignment is
evaluated by examining the number of zeroes in the lower order bits. The minimum
alignment is 256 bytes; therefore, bits 0 through 7 must always return '0' when read.
Detailed description can be found in Chapter 4. This area is used to hold the control
structures and the Interrupt table that are accessed by both the Host Controller and the
Host Controller Driver.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCHCCA: [BAR0] + 18h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
hccabase
0
Bit
Range
0
0
0
4
0
0
0
0
0
0
0
0
0
reserved_7_0
31
Default &
Access
Description
31: 8
0h
RW
Host Controller Communication Area Base (hccabase): This is the base address of
the Host Controller Communication Area
7: 0
0h
RO
reserved_7_0 (reserved_7_0): Reserved bits.
These bits are reserved and should be set to zero.
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.3.8
Host Controller Current Isochronous or Interrupt Endpoint
(HCPRDCURED)—Offset 1Ch
The HcPeriodCurrentED register contains the physical address of the current
Isochronous or Interrupt Endpoint Descriptor.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCPRDCURED: [BAR0] + 1Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
Bit
Range
16.6.3.9
0
0
0
reserved_3_0
period_cur_ed
0
28
Default &
Access
Description
31: 4
0h
RO
Period Current ED (period_cur_ed): This is used by HC to point to the head of one of
the Periodic lists which will be processed in the current Frame. The content of this
register is updated by HC after a periodic ED has been processed. HCD may read the
content in determining which ED is currently being processed at the time of reading.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
Host Controller Current First Control Endpoint (HCCTRLHEADED)—
Offset 20h
The HCCTRLHEADED register contains the physical address of the first Endpoint
Descriptor of the Control list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCCTRLHEADED: [BAR0] + 20h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
ctrl_head_ed
0
28
August 2015
Document Number: 329676-005US
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
reserved_3_0
31
Intel® Quark™ SoC X1000
Datasheet
577
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
16.6.3.10
Default &
Access
Description
31: 4
0h
RW
Control Head ED (ctrl_head_ed): HC traverses the Control list starting with the
HCCTRLHEADED pointer. The content is loaded from HCCA during the initialization of
HC.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
Host Controller Current Control Endpoint (HCCTRLCURED)—Offset 24h
The HCCTRLCURED register contains the physical address of the current Endpoint
Descriptor of the Control list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCCTRLCURED: [BAR0] + 24h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
ctrl_cur_ed
0
28
Bit
Range
16.6.3.11
0
0
reserved_3_0
31
Default &
Access
Description
31: 4
0h
RW
Control Current ED (ctrl_cur_ed): This pointer is advanced to the next ED after
serving the present one. HC will continue processing the list from where it left off in the
last Frame. When it reaches the end of the Control list, HC checks the ctrllist_filled of in
HCCMDSTATUS. If set, it copies the content of HCCTRLHEADED to HCCTRLCURED and
clears the bit. If not set, it does nothing. HCD is allowed to modify this register only
when the ctrllist_enable of HCCONTROL is cleared. When set, HCD only reads the
instantaneous value of this register. Initially, this is set to zero to indicate the end of the
Control list.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
Host Controller First Bulk Endpoint (HCBULKHEADED)—Offset 28h
The HCBULKHEADED register contains the physical address of the first Endpoint
Descriptor of the Bulk list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCBULKHEADED: [BAR0] + 28h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
Bit
Range
16.6.3.12
0
0
0
reserved_3_0
bulk_head_ed
0
28
Default &
Access
Description
31: 4
0h
RW
Bulk Head ED (bulk_head_ed): HC traverses the Bulk list starting with the
HCBULKHEADED pointer. The content is loaded from HCCA during the initialization of
HC.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
Host Controller Current Bulk Endpoint (HCBULKCURED)—Offset 2Ch
The HCBULKCURED register contains the physical address of the current endpoint of
the Bulk list. As the Bulk list will be served in a round-robin fashion, the endpoints will
be ordered according to their insertion to the list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCBULKCURED: [BAR0] + 2Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
bulk_cur_ed
0
28
Bit
Range
0
0
0
4
0
0
0
0
0
0
0
0
0
reserved_3_0
31
Default &
Access
Description
31: 4
0h
RW
Bulk Current ED (bulk_cur_ed): This is advanced to the next ED after the HC has
served the present one. HC continues processing the list from where it left off in the last
Frame. When it reaches the end of the Bulk list, HC checks the ctrllist_filled of
HCCONTROL. If set, it copies the content of HCBULKHEADED to HCBULKCURED and
clears the bit. If it is not set, it does nothing. HCD is only allowed to modify this register
when the bulklist_enable of HCCONTROL is cleared. When set, the HCD only reads the
instantaneous value of this register. This is initially set to zero to indicate the end of the
Bulk list.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
579
Intel® Quark™ SoC X1000—USB 2.0
16.6.3.13
Host Controller Last Completed Descriptor (HCDONEHEAD)—Offset
30h
The HCDONEHEAD register contains the physical address of the last completed Transfer
Descriptor that was added to the Done queue. In normal operation, the Host Controller
Driver should not need to read this register as its content is periodically written to the
HCCA.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCDONEHEAD: [BAR0] + 30h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
donehead
0
28
Bit
Range
16.6.3.14
Default &
Access
0
0
0
reserved_3_0
31
Description
31: 4
0h
RO
Done Head (donehead): When a TD is completed, HC writes the content of
HCDONEHEAD to the NextTD field of the TD. HC then overwrites the content of
HCDONEHEAD with the address of this TD. This is set to zero whenever HC writes the
content of this register to HCCA. It also sets the wrback_donehead of HCINTRSTATUS.
3: 0
0h
RO
reserved_3_0 (reserved_3_0): Reserved bits.
These bits are reserved and should be set to zero.
Host Controller Frame Interval (HCFMINTERVAL)—Offset 34h
The HCFMINTERVAL register contains a 14-bit value which indicates the bit time
interval in a Frame, (i.e., between two consecutive SOFs), and a 15-bit value indicating
the Full Speed maximum packet size that the Host Controller may transmit or receive
without causing scheduling overrun. The Host Controller Driver may carry out minor
adjustment on the fm_interval by writing a new value over the present one at each
SOF. This provides the programmability necessary for the Host Controller to
synchronize with an external clocking resource and to adjust any unknown local clock
offset.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCFMINTERVAL: [BAR0] + 34h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00002EDFh
Intel® Quark™ SoC X1000
Datasheet
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August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
0
0
0
24
0
0
0
0
Bit
Range
0
0
0
0
16
0
0
0
0
12
0
1
0
8
1
1
1
0
reserved_15_14
0
Default &
Access
4
1
1
0
1
0
1
1
1
1
Description
0h
RW
Frame Interval Toggle (fm_interval_tgl): HCD toggles this bit whenever it loads a
new value to fm_interval.
30: 16
0h
RW
FS Largest Data Packet (fsmps): This field specifies a value which is loaded into the
Largest Data Packet Counter at the beginning of each frame. The counter value
represents the largest amount of data in bits which can be sent or received by the HC in
a single transaction at any given time without causing scheduling overrun. The field
value is calculated by the HCD.
15: 14
0h
RO
reserved_15_14 (reserved_15_14): Reserved bits.
These bits are reserved and should be set to zero.
31
Frame Interval (fm_interval): This specifies the interval between two consecutive
SOFs in bit times. The nominal value is set to be 11,999.HCD should store the current
value of this field before resetting HC. By setting the hcreset field of HCCMDSTATUS as
this will cause the HC to reset this field to its nominal value. HCD may choose to restore
the stored value upon the completion of the Reset sequence.
2EDFh
RW
13: 0
16.6.3.15
20
fsmps
fm_interval_tgl
0
28
fm_interval
31
Host Controller Remaining Frame (HCFMREMAINING)—Offset 38h
The HCFMREMAINING register is a 14-bit down counter showing the bit time remaining
in the current Frame. NOTE: In OpenHCI 1.0a, the Frame Remaining and Frame
Remaining Toggle bits in the HCFMREMAINING register are read-only to the Host
Controller Driver. However, it is allowed to write to these bits for debugging purposes.
Though these bits are writable, the Host Controller Driver must not write into these
bits. Doing so yields undefined results.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCFMREMAINING: [BAR0] + 38h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
August 2015
Document Number: 329676-005US
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
fm_remaining
0
24
fm_remaining_tgl
0
28
reserved_30_14
31
Intel® Quark™ SoC X1000
Datasheet
581
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
31
30: 14
13: 0
16.6.3.16
Description
0h
RW
Frame Remaining Toggle (fm_remaining_tgl): This bit is loaded from the
fm_interval_tgl field of fm_interval whenever fm_remaining reaches 0. This bit is used
by HCD for the synchronization between fm_interval and fm_remaining.
NOTE: Though these bits are writable, the Host Controller Driver must not write into
these bits. Doing so yields undefined results.
0h
RO
reserved_30_14 (reserved_30_14): Reserved bits.
These bits are reserved and should be set to zero.
0h
RW
Frame Remaining (fm_remaining): This counter is decremented at each bit time.
When it reaches zero, it is reset by loading the fm_interval value specified in fm_interval
at the next bit time boundary. When entering the USBOPERATIONAL state, HC re-loads
the content with the fm_interval of HCFMINTERVAL and uses the updated value from the
next SOF.
NOTE: Though these bits are writable, the Host Controller Driver must not write into
these bits. Doing so yields undefined results.
Host Controller Frame Number (HCFMNUMBER)—Offset 3Ch
The HCFMNUMBER register is a 16-bit counter. It provides a timing reference among
events happening in the Host Controller and the Host Controller Driver. The Host
Controller Driver may use the 16-bit value specified in this register and generate a 32bit frame number without requiring frequent access to the register. NOTE: In OpenHCI
1.0a, the Frame Number bits in the HCFMNUMBER register are read-only to the Host
Controller Driver. However, it is allowed to write to these bits for debugging purposes.
Though these bits are writable, the Host Controller Driver must not write into these
bits. Doing so yields undefined results.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCFMNUMBER: [BAR0] + 3Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
fmnumber
reserved_31_16
0
Bit
Range
Default &
Access
31: 16
0h
RO
reserved_31_16 (reserved_31_16): Reserved bits.
These bits are reserved and should be set to zero.
0h
RW
Frame Number (fmnumber): This is incremented when fm_remaining is re-loaded. It
will be rolled over to 0 after FFFF. When entering the USBOPERATIONAL state, this will
be incremented automatically. The content will be written to HCCA after HC has
incremented the FrameNumber at each frame boundary and sent a SOF but before HC
reads the first ED in that Frame. After writing to HCCA, HC will set the start_of_frame in
HCINTRSTATUS.
NOTE: Though these bits are writable, the Host Controller Driver must not write into
these bits. Doing so yields undefined results.
15: 0
Intel® Quark™ SoC X1000
Datasheet
582
Description
August 2015
Document Number: 329676-005US
USB 2.0—Intel® Quark™ SoC X1000
16.6.3.17
Host Controller Periodic List Start (HCPERIODICSTART)—Offset 40h
The HcPeriodicStart register has a 14-bit programmable value which determines when
is the earliest time HC should start processing the periodic list.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCPERIODICSTART: [BAR0] + 40h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
reserved_31_14
0
28
0
0
0
0
0
0
0
0
0
Bit
Range
Default &
Access
31: 14
0h
RO
reserved_31_14 (reserved_31_14): Reserved bits.
These bits are reserved and should be set to zero.
0h
RW
Periodic Start (periodic_start): After hardware reset, this field is cleared. This is
then set by HCD during the HC initialization. The value is calculated roughly as 10% off
from fm_interval. A typical value will be h3E67. When fm_remaining reaches the value
specified, processing of the periodic lists will have priority over Control/Bulk processing.
HC will therefore start processing the Interrupt list after completing the current Control
or Bulk transaction that is in progress.
13: 0
16.6.3.18
4
periodic_start
31
Description
Host Controller LS Threshold (HCLSTHRESHOLD)—Offset 44h
The HcLSThreshold register contains an 11-bit value used by the Host Controller to
determine whether to commit to the transfer of a maximum of 8-byte LS packet before
EOF. Neither the Host Controller nor the Host Controller Driver is allowed to change this
value.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCLSTHRESHOLD: [BAR0] + 44h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000628h
0
0
0
24
0
0
0
0
20
0
0
reserved_31_12
0
28
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Document Number: 329676-005US
0
0
16
0
0
0
0
12
0
0
0
0
8
0
1
1
0
4
0
0
1
0
0
1
0
0
0
ls_threshold
31
Intel® Quark™ SoC X1000
Datasheet
583
Intel® Quark™ SoC X1000—USB 2.0
Bit
Range
Default &
Access
31: 12
0h
RO
16.6.3.19
reserved_31_12 (reserved_31_12): Reserved bits.
These bits are reserved and should be set to zero.
LS Threshold (ls_threshold): This field contains a value which is compared to the
fm_remaining field prior to initiating a Low Speed transaction. The transaction is started
only if fm_remaining this field. The value is calculated by HCD with the consideration of
transmission and setup overhead.
NOTE: Neither the Host Controller nor the Host Controller Driver are allowed to change
this value.
0628h
RW
11: 0
Description
Host Controller Root Hub Descriptor A (HCRHDESPA)—Offset 48h
The HCRHDESPA register is the first register of two describing the characteristics of the
Root Hub.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCRHDESPA: [BAR0] + 48h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 02000902h
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
4
0
0
0
0
0
0
0
1
0
ndp
1
pwr_switch_mode
0
8
device_type
0
12
no_pwr_switching
0
16
no_overcur_prot
0
20
overcur_prot_mode
0
24
pwron_to_pwrgood_time
0
28
reserved_23_13
31
Bit
Range
Default &
Access
Description
31: 24
02h
RW
Power On To Power Good Time (pwron_to_pwrgood_time): This byte specifies
the duration HCD has to wait before accessing a powered-on port of the Root Hub. It is
implementation-specific. The unit of time is 2ms. The duration is calculated as
pwron_to_pwrgood_time*2ms.
23: 13
0h
RO
reserved_23_13 (reserved_23_13): Reserved bits.
These bits are reserved and should be set to zero.
0h
RW
No Over Current Protection (no_overcur_prot): This bit describes how the
overcurrent status for the Root Hub ports is reported. When this bit is cleared, the
overcur_prot_mode field specifies global or per-port reporting.
0: Over-current status is reported collectively for all downstream ports
1: No overcurrent protection supported
11
1h
RW
Over Current Protection Mode (overcur_prot_mode): This bit describes how the
overcurrent status for the Root Hub ports is reported. At reset, this field should reflect
the same mode as pwr_switch_mode. This field is valid only if the no_overcur_prot field
is cleared.
0: over-current status is reported collectively for all downstream ports
1: over-current status is reported on a per-port basis
10
0h
RO
Device Type (device_type): This bit specifies that the Root Hub is not a compound
device. The Root Hub is not permitted to be a compound device. This field should always
read/write 0.
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Bit
Range
Default &
Access
Description
0h
RW
No Power Switching (no_pwr_switching): These bits are used to specify whether
power switching is supported or port are always powered. It is implementation-specific.
When this bit is cleared, the pwr_switch_mode specifies global or per-port switching.
0: Ports are power switched
1: Ports are always powered on when the HC is powered on
8
1h
RW
Power Switching Mode (pwr_switch_mode): This bit is used to specify how the
power switching of the Root Hub ports is controlled. It is implementation-specific. This
field is only valid if the no_pwr_switching field is cleared.
0: all ports are powered at the same time.
1: each port is powered individually. This mode allows port power to be controlled by
either the global switch or per-port switching. If the port_pwr_ctrlmask bit is set, the
port responds only to port power commands (Set/ClearPortPower). If the port mask is
cleared, then the port is controlled only by the global power switch (Set/
ClearGlobalPower).
7: 0
02h
RO
Number Downstream Ports (ndp): These bits specify the number of downstream
ports (ndp) supported by the Root Hub. It is implementation-specific. The minimum
number of ports is 1.
9
16.6.3.20
Host Controller Root Hub Descriptor B (HCRHDESPB)—Offset 4Ch
The HCRHDESPB register is the second register of two describing the characteristics of
the Root Hub. These fields are written during initialization to correspond with the
system implementation.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCRHDESPB: [BAR0] + 4Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
reserved_1
0
device_removable
0
reserved_16_3
28
0
reserved_31_18
0
port_pwr_ctrlmask
31
Bit
Range
Default &
Access
31: 19
0h
RO
reserved_31_18 (reserved_31_18): Reserved bits.
These bits are reserved and should be set to zero.
18: 17
0h
RW
Port Power Control Mask (port_pwr_ctrlmask): Each bit indicates if a port is
affected by a global power control command when pwr_switch_mode is set. When set,
the port's power state is only affected by per-port power control (Set/ClearPortPower).
When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower).
If the device is configured to global switching mode (pwr_switch_mode=0), this field is
not valid.
bit 0: Reserved
bit 1: Ganged-power mask on Port #1
bit 2: Ganged-power mask on Port #2
NOTE: Per Port Power Control is supported
16: 3
0h
RO
reserved_16_3 (reserved_16_3): Reserved bits.
These bits are reserved and should be set to zero.
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Description
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16.6.3.21
Bit
Range
Default &
Access
Description
2: 1
0h
RW
Device Removable (device_removable): Each bit is dedicated to a port of the Root
Hub. When cleared, the attached device is removable. When set, the attached device is
not removable.
bit 0: Reserved
bit 1: Device attached to Port #1
bit 2: Device attached to Port #2
0
0h
RO
reserved_1 (reserved_1): Reserved bit. These bits are reserved and should be set to
zero.
Host Controller Root Hub Status (HCRHSTATUS)—Offset 50h
The HCRHSTATUS register is divided into two parts. The lower word of a Dword
represents the Hub Status field and the upper word represents the Hub Status Change
field. Reserved bits should always be written '0'.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCRHSTATUS: [BAR0] + 50h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
0
Bit
Range
31
30: 18
17
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Default &
Access
20
0
0
0
0
16
0
0
12
0
0
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
overcur_ind
0
local_pwrsts
0
reserved_14_2
24
0
dev_rmtwkup_enb
0
reserved_30_18
0
overcur_ind_change
28
0
clr_rmtwkup_enb
0
local_pwrsts_change
31
Description
0h
WO
Clear Remote Wakeup Enable (clr_rmtwkup_enb): Writing a '1' clears
dev_rmtwkup_enb. Writing a '0' has no effect.
0h
RO
reserved_30_18 (reserved_30_18): Reserved bits.
These bits are reserved and should be set to zero.
0h
RW/1S
Over Current Indicator Change (overcur_ind_change): This bit is set by hardware
when a change has occurred to the OCI field of this register. The HCD clears this bit by
writing a 1.Writing a 0 has no effect.
0h
RW/1S
Local Power Status Change / SetGlobalPower (local_pwrsts_change): (read)
Local Power Status Change.
The Root Hub does not support the local power status feature and this bit is always read
as 0.
(write) SetGlobalPower.
In global power mode (pwr_switch_mode=0), this bit is written to 1 to turn on power to
all ports (clear pps).
In per-port power mode, it sets pps only on ports whose port_pwr_ctrlmask bit is not
set.
Writing a 0 has no effect.
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Bit
Range
Default &
Access
Device Remote Wakeup Enable / SetRemoteWakeupEnable
(dev_rmtwkup_enb): (read) Device Remote Wakeup Enable.
This bit enables a csc bit as a resume event, causing a USBSUSPEND to USBRESUME
state transition and setting the resume_detected interrupt.
0: csc is not a remote wakeup event.
1: csc is a remote wakeup event.
(write) SetRemoteWakeupEnable.
Writing a '1' sets dev_rmtwkup_enb. Writing a '0' has no effect.
15
0h
RW/1S
14: 2
0h
RO
reserved_14_2 (reserved_14_2): Reserved bits.
These bits are reserved and should be set to zero.
1
0h
RO
Over Current Indicator (overcur_ind): This bit reports overcurrent conditions when
the global reporting is implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal. If per-port overcurrent protection is
implemented this bit is always 0
0h
RW/1S
Local Power Status / ClearGlobalPower (local_pwrsts): (read)Local Power Status.
The Root Hub does not support the local power status feature; thus, this bit is always
read as 0.
(write) ClearGlobalPower.
In global power mode (pwr_switch_mode=0), this bit is written to 1 to turn off power to
all ports (clear pps).
In per-port power mode, it clears pps only on ports whose port_pwr_ctrlmask bit is not
set.
Writing a 0 has no effect.
0
16.6.3.22
Description
Host Controller Root Hub Port Status (HCRHPORTSTS)—Offset 54h
The HCRHPORTSTS[1:ndp] register is used to control and report port events on a perport basis. ndp represents the number of HCRHPORTSTS registers that are
implemented in hardware. The lower word is used to reflect the port status, whereas
the upper word reflects the status change bits. Some status bits are implemented with
special write behavior (see below). If a transaction (token through handshake) is in
progress when a write to change port status occurs, the resulting port status change
must be postponed until the transaction completes. Reserved bits should always be
written '0'.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
HCRHPORTSTS: [BAR0] + 54h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:4] + 10h
Default: 00000000h
Bit
Range
Default &
Access
31: 21
0h
RO
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ccs
0
pss
0
pes
0
prs
0
0
poci
0
4
reserved_7_5
0
pps
0
8
lsda
0
12
reserved_15_10
0
csc
0
pesc
0
16
ocic
0
20
pssc
0
24
reserved_31_21
0
28
prsc
31
Description
reserved_31_21 (reserved_31_21): Reserved bits.
These bits are reserved and should be set to zero.
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Bit
Range
Default &
Access
Description
20
0b
RW/1C
Port Reset Status Change (prsc): This bit is set at the end of the 10-ms port reset
signal. The HCD writes a 1 to clear this bit. Writing a 0 has no effect.
0: port reset is not complete
1: port reset is complete
19
0b
RW/1C
Port Over Current Indicator Change (ocic): This bit is valid only if overcurrent
conditions are reported on a per-port basis. This bit is set when Root Hub changes the
poci bit. The HCD writes a 1 to clear this bit. Writing a 0 has no effect.
0: no change in poci
1: poci has changed
18
0b
RW/1C
Port Suspend Status Change (pssc): This bit is set when the full resume sequence
has been completed. This sequence includes the 20-s resume pulse, LS EOP, and 3-ms
resychronization delay. The HCD writes a 1 to clear this bit. Writing a 0 has no effect.
This bit is also cleared when prsc is set.
0: resume is not completed
1: resume completed
17
0b
RW/1C
Port Enable Status Change (pesc): This bit is set when hardware events cause the
pes bit to be cleared. Changes from HCD writes do not set this bit. The HCD writes a 1 to
clear this bit. Writing a 0 has no effect.
0: no change in pes
1: change in pes
0b
RW/1C
Connect Status Change (csc): This bit is set whenever a connect or disconnect event
occurs. The HCD writes a 1 to clear this bit. Writing a 0 has no effect. If ccs is cleared
when a SetPortReset, SetPortEnable, or SetPortSuspend write occurs, this bit is set to
force the driver to re-evaluate the connection status since these writes should not occur
if the port is disconnected.
0: no change in ccs
1 = change in ccs
Note: If the device_removable[ndp] bit is set, this bit is set only after a Root Hub reset
to inform the system that the device is attached.
16
15: 10
0h
RO
reserved_15_10 (reserved_15_10): Reserved bits.
These bits are reserved and should be set to zero.
0b
RW/1C
Speed Device Attached / Clear Port Power (lsda): (read) Low or Full Speed Device
Attached.
This bit indicates the speed of the device attached to this port. When set, a Low Speed
device is attached to this port. When clear, a Full Speed device is attached to this port.
This field is valid only when the ccs is set.
0: full speed device attached
1: low speed device attached
(write) ClearPortPower.
The HCD clears the pps bit by writing a 1 to this bit. Writing a 0 has no effect.
8
0b
RW/1C
Port Power Status / Set Port Power (pps): (read) Port Power Status.
This bit reflects the port power status, regardless of the type of power switching
implemented. This bit is cleared if an overcurrent condition is detected. HCD sets this bit
by writing SetPortPower or SetGlobalPower. HCD clears this bit by writing
ClearPortPower or ClearGlobalPower. Which power control switches are enabled is
determined by pwr_switch_mode and PortPortControlMask[ndp]. In global switching
mode , only Set/ClearGlobalPower controls this bit. In per-port power switching
(pwr_switch_mode=1), if the port_pwr_ctrlmask[ndp] bit for the port is set, only Set/
ClearPortPower commands are enabled. If the mask is not set, only Set/
ClearGlobalPower commands are enabled. When port power is disabled, ccs, pes, pss,
and prs should be reset.
0: port power is off
1: port power is on
(write) SetPortPower.
The HCD writes a 1 to set the pps bit. Writing a 0 has no effect.
7: 5
0h
RO
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reserved_7_5 (reserved_7_5): Reserved bits.
These bits are reserved and should be set to zero.
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Bit
Range
4
3
2
1
0
Default &
Access
Description
0b
RW/1C
Port Reset Status / Set Port Reset (prs): (read) Port Reset Status.
When this bit is set by a write to SetPortReset, port reset signaling is asserted. When
reset is completed, this bit is cleared when prsc is set. This bit cannot be set if ccs is
cleared.
0: port reset signal is not active
1: port reset signal is active
(write) SetPortReset.
The HCD sets the port reset signaling by writing a 1 to this bit. Writing a 0 has no effect.
If ccs is cleared, this write does not set prs, but instead sets csc. This informs the driver
that it attempted to reset a disconnected port.
0b
RW/1C
Port Over Current Indicator / Clear Suspend Status (poci): (read) Port Over
Current Indicator.
This bit is only valid when the Root Hub is configured in such a way that overcurrent
conditions are reported on a per-port basis. If per-port overcurrent reporting is not
supported, this bit is set to 0. If cleared, all power operations are normal for this port. If
set an overcurrent condition exists on this port. This bit always reflects the overcurrent
input signal
0: no overcurrent condition.
1: overcurrent condition detected.
(write) ClearSuspendStatus.
The HCD writes a 1 to initiate a resume. Writing a 0 has no effect. A resume is initiated
only if pss is set.
0b
RW/1C
Port Suspend Status / Set Port Suspend (pss): Port Suspend Status.
This bit indicates the port is suspended or in the resume sequence. It is set by a
SetSuspendState write and cleared when pssc is set at the end of the resume interval.
This bit cannot be set if ccs is cleared. This bit is also cleared when prsc is set at the end
of the port reset or when the HC is placed in the USBRESUME state. If an upstream
resume is in progress, it should propagate to the HC.
0: port is not suspended
1: port is suspended
(write) SetPortSuspend.
The HCD sets the pss bit by writing a 1 to this bit. Writing a 0 has no effect. If ccs is
cleared, this write does not set pss; instead it sets csc. This informs the driver that it
attempted to suspend a disconnected port.
0b
RW/1C
Port Enable Status / Set Port Enable (pes): (read) Port Enable Status.
This bit indicates whether the port is enabled or disabled. The Root Hub may clear this
bit when an overcurrent condition, disconnect event, switched-off power, or operational
bus error such as babble is detected. This change also causes pesc to be set. HCD sets
this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot
be set when ccs is cleared. This bit is also set, if not already, at the completion of a port
reset when prsc is set or port suspend when pssc is set.
0: port is disabled
1: port is enabled
(write) SetPortEnable.
The HCD sets pes by writing a 1. Writing a 0 has no effect. If ccs is cleared, this write
does not set pes, but instead sets csc. This informs the driver that it attempted to
enable a disconnected port.
0b
RW/1C
Current Connect Status / Clear Port Enable (ccs): (read) Current Connect Status.
This bit reflects the current state of the downstream port.
0: no device connected
1: device connected
(write) ClearPortEnable
The HCD writes a 1 to this bit to clear the pes bit. Writing a 0 has no effect. The ccs is
not affected by any write.
Note: This bit is always read 1 when the attached device is non-removable
(device_removable[ndp]).
§§
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Intel® Quark™ SoC X1000—USB 2.0
Intel® Quark™ SoC X1000
Datasheet
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.0
SDIO/SD/eMMC
The Intel® Quark™ SoC X1000 provides an SDIO/SD/eMMC controller that supports a
single port configurable as:
• One SDIO 3.0 interface
• One SD 3.0 interface
• One eMMC 4.41 interface
3
17.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 109.
SDIO/SD/eMMC Interface Signals
Signal Name
SD_CLK
Direction/
Type
O
3.3V
I/O
SD_DATA[7:0]
3.3V
SD_CD_B
3.3V
I
Description
SD Card Clock
Clock frequency up to 50 MHz.
SD Card Data
Bidirectional port used to transfer data to and from SD/eMMC
card.
By default, after power up or reset, only D[0] is used for data
transfer. A wider data bus can be configured for data transfer,
using D[0]-D[7].
SD Card Detect
Active low when a card is present. Floating (pulled high with
internal PU) when a card is not present.
SD_CMD
I/O
MG
SD Card Command
This signal is used for card initialization and transfer of
commands. It has two modes—open-drain for initialization, and
push-pull for fast command transfer.
SD_WP
I
MG
SD Card Write Protect
Active high to protect from write.
SD_LED
O
MG
SD Card Access LED Control
Controls the LED to indicate that the card is being accessed
SD_PWR
O
MG
SD Card Power Supply Control
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17.2
Features
17.2.1
SDIO/SD/eMMC Features
Table 110 summarizes the SDIO/SD/eMMC supported/non-supported features.
Table 110.
SDIO/SD/eMMC Features
Features
Supported
Meets SD Memory Card Specification version 3.0
Yes
Meets SD Host Controller Standard Specification Version 3.0
Yes
Meets SDIO card specification version 3.0
Yes
Meets eMMC Specification version 4.41
Yes
Supports both DMA and Non-DMA mode of operation
Yes
Supports SDMA
Yes
Supports ADMA1 and ADMA2
Yes
eMMC supports 1 bit, 4 bit and 8 bit bus modes
Yes
SD/SDIO supports 1 bit and 4 bit bus modes
Yes
SDXC Capacity up to 2TB
Yes
High Speed (SD Clock up to 50 MHz - 25 MByte/s for SDIO/SD and 50 MByte/s for
eMMC)
Yes
Integrated ADMA Controller
Yes
SD SPI mode
Yes
Multi SD/SDIO card Slots
No
Boot OS from SD/eMMC device (see Note)
Yes
SDIO Dual Voltage support 1.8V/3.3V
No
SDIO/SD UHS-I Support
No
Wakeup On Card Insertion
No
Note:
1. Must pair together with SPI chip.
2. Refer to the Intel® X1000 – Board Support Package (BSP) UEFI EMMC Patch on eMMC enabling for software
portion.
17.2.2
SD 3.0/ SDIO 3.0 / eMMC 4.41 Interfaces
This section provides a very high level overview of the SD, SDIO, eMMC 4.41
specification. Refer to the SD and eMMC specification for complete details.
17.2.2.1
SD 3.0 Bus Topology
The SD Memory Card bus has a single master, single slave (card), synchronous
topology (refer to Figure 33). During the initialization process, commands are sent to
the card allowing the application to detect the card and assign logical addresses to the
physical slot. All data communication in the Card Identification Mode uses the
command line (CMD) only.
The SD bus allows dynamic configuration of the number of data lines. After power up,
by default, the SD Memory Card uses only D[0] for data transfer. After initialization the
host can change the bus width (number of active data lines). This feature allows easy
trade off between hardware cost and system performance. Note that while D[1:3] are
not in use, the related host’s data lines should be in tri-state (input mode).
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Figure 33.
SD Memory Card Bus Topology
CLK
VDD
SD Host
SD
Memory Card
Vss
D[3:0]
CMD
17.2.2.2
SDIO 3.0 Interface
The SDIO card interface is very much like the SD Memory Card interface. The SoC
supports one SDIO card slot.
Figure 34.
SDIO Card Bus Topology
SD Host
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CLK
CLK
CMD
CMD
D[0]
D[0]
D[1]
D[1]/Interrupt
D[2]
D[2]/Wait for Read
D[3]
CD/D[3]
SD I/O Card
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17.2.2.3
eMMC Interface
Figure 35.
eMMC Interface
CLK
CMD
eMMC Host
eMMC Device
D[0:7]
RST#
17.2.3
SDIO/SD/eMMC Host Controller
The Secure Digital Host Controller 3.0 specification defines a standardized host
controller for interfacing to eMMC devices, as well as Secure Digital memory and I/O
cards. The specification encompasses the following:
• A register map and register set
• Data buffer model
• Data movement model, including both Programmed I/O (PIO) and Direct Memory
Access (DMA)
• Three different DMA modes:
— Single DMA (SDMA)
— Advanced DMA Mode 1; this is linked list DMA with the restriction that data
buffers must reside at 4k boundaries.
— Advanced DMA Mode 2; this is linked list DMA with the restriction of 4k aligned
data buffers removed; data buffers may reside at any arbitrary alignment.
64-bit addressing is also supported.
• Interrupt model
• Suspend and resume mechanism
• Power state definition
• Method for automatic generation of STOP_TRANSMISSION commands (Auto
CMD12)
• Test registers
In short, the SD Host Controller specification defines a standard software model for
accessing SD/SDIO/eMMC devices, and makes it possible for standards-compliant host
controllers to work with off-the-shelf device drivers.
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.2.3.1
SD DMA
A new DMA transfer algorithm, called ADMA (Advanced DMA), is defined in the SD Host
Controller Standard Specification Version 2.00. The DMA algorithm defined in the SD
Host Controller Standard Specification Version 1.00 is called SDMA (Single Operation
DMA). SDMA had the disadvantage that a DMA Interrupt generated at every page
boundary disturbs the CPU to reprogram the new system address. This SDMA algorithm
forms a performance bottleneck by interruption at every page boundary. Only one SD
command transaction can be executed per a SDMA operation.
ADMA adopts a scatter-gather DMA algorithm, so that higher data transfer speed is
available. The Host Driver can program a list of data transfers between system memory
and SD card to the Descriptor Table before executing ADMA. It enables ADMA to
operate without interrupting the Host Driver.
There are two types of ADMA; ADMA1 and ADMA2. ADMA1 can support data transfer of
only 4 KByte aligned data in system memory. ADMA2 improves the restriction so that
data of any location and any size can be transferred in system memory. The format of
Descriptor Table is different between them. The Host Controller Specification Ver2.00
defines ADMA2 as standard ADMA and recommends supporting ADMA2 rather than
ADMA1.
The SDIO/SD/eMMC controller supports all three flavors of DMA described in the SD
Host Controller 2.0 specification - SDMA, ADMA1, and ADMA2.
Note:
Although the SD Host Controller Standard Specification Version 3.00 states that ADMA1
is not supported in Standard Host Controller versions 3.0 and latter, the SoC SDIO/SD/
eMMC controller supports both ADMA1 and ADMA2.
17.3
References
The SDIO/SD/eMMC controller is a Secure Digital I/O (SDIO), Secure Digital (SD),
MultiMediaCard (eMMC) host controller that is configured to comply with:
• SD Specification Part 1 Physical Layer Specification version 3.00, April 16, 2009
https://www.sdcard.org
• SD Specification Part E1 SDIO Specification version 3.00, December 16, 2010
https://www.sdcard.org
• SD Specification Part A2 SD Host Controller Standard Specification version 3.00,
February 18, 2010 https://www.sdcard.org
• Embedded MultiMediaCard (eMMC) Product Standard v4.41, JESD84-A441 http://
www.jedec.org/.
17.4
Register Map
See Chapter 5.0, “Register Access Methods” for additional information.
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Figure 36.
SDIO/SD/eMMC Register Map
PCI Space
CPU
Core
Host Bridge
D:0,F:0
PCI
CAM
(I/O)
Bus 0
SDIO/
eMMC PCI
Headers
D:20,F:0
PCI
ECAM
(Mem)
I2C*/GPIO F:2
PCIe*
D:23
SPI1 F:1
IO Fabric
D:21
SPI0 F:0
RP0 F:0
RP0 F:1
BAR
Legacy Bridge
D:31, F:0
SDIO/eMMC
Mem
Registers
SDIO/eMMC F:0
HSUART0 F:1
EHCI Host F:3
OCHI Host F:4
HSUART1 F:5
IO Fabric D:20
USB Device F:2
Memory
Space
MAC0 F:6
MAC1 F:7
17.5
PCI Configuration Registers
Table 111.
Summary of PCI Configuration Registers—0/20/0
Offset Start
Offset End
Default
Value
Register ID—Description
0h
1h
“Vendor ID (VENDOR_ID)—Offset 0h” on page 597
8086h
2h
3h
“Device ID (DEVICE_ID)—Offset 2h” on page 598
08A7h
4h
5h
“Command Register (COMMAND_REGISTER)—Offset 4h” on page 598
0000h
6h
7h
“Status Register (STATUS)—Offset 6h” on page 599
0010h
8h
Bh
“Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h” on page 599
08050110h
Ch
Ch
“Cache Line Size (CACHE_LINE_SIZE)—Offset Ch” on page 600
00h
Dh
Dh
“Latency Timer (LATENCY_TIMER)—Offset Dh” on page 600
00h
Eh
Eh
“Header Type (HEADER_TYPE)—Offset Eh” on page 601
80h
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Table 111.
Offset Start
Summary of PCI Configuration Registers—0/20/0 (Continued)
Offset End
Default
Value
Register ID—Description
Fh
Fh
“BIST (BIST)—Offset Fh” on page 601
00h
10h
13h
“Base Address Register (BAR0)—Offset 10h” on page 602
00000000h
28h
2Bh
“Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h” on page 602
00000000h
2Ch
2Dh
“Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch” on page 603
0000h
2Eh
2Fh
“Subsystem ID (SUB_SYS_ID)—Offset 2Eh” on page 603
0000h
30h
33h
“Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset 30h” on page 603
00000000h
34h
37h
“Capabilities Pointer (CAP_POINTER)—Offset 34h” on page 604
00000080h
3Ch
3Ch
“Interrupt Line Register (INTR_LINE)—Offset 3Ch” on page 604
00h
3Dh
3Dh
“Interrupt Pin Register (INTR_PIN)—Offset 3Dh” on page 605
00h
3Eh
3Eh
“MIN_GNT (MIN_GNT)—Offset 3Eh” on page 605
00h
3Fh
3Fh
“MAX_LAT (MAX_LAT)—Offset 3Fh” on page 605
00h
80h
80h
“Capability ID (PM_CAP_ID)—Offset 80h” on page 606
01h
81h
81h
“Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h” on page 606
A0h
82h
83h
“Power Management Capabilities (PMC)—Offset 82h” on page 606
4803h
84h
85h
“Power Management Control/Status Register (PMCSR)—Offset 84h” on page 607
0008h
86h
“PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—Offset 86h” on
page 608
00h
87h
87h
“Power Management Data Register (DATA_REGISTER)—Offset 87h” on page 608
00h
A0h
A0h
“Capability ID (MSI_CAP_ID)—Offset A0h” on page 609
05h
A1h
A1h
“Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h” on page 609
00h
A2h
A3h
“Message Control (MESSAGE_CTRL)—Offset A2h” on page 609
0100h
A4h
A7h
“Message Address (MESSAGE_ADDR)—Offset A4h” on page 610
00000000h
A8h
A9h
“Message Data (MESSAGE_DATA)—Offset A8h” on page 610
0000h
ACh
AFh
“Mask Bits for MSI (PER_VEC_MASK)—Offset ACh” on page 611
00000000h
B0h
B3h
“Pending Bits for MSI (PER_VEC_PEND)—Offset B0h” on page 611
00000000h
86h
17.5.1
Vendor ID (VENDOR_ID)—Offset 0h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
VENDOR_ID: [B:0, D:20, F:0] + 0h
Default: 8086h
15
0
0
0
8
0
0
0
4
0
1
0
0
0
0
0
1
1
0
value
1
12
Bit
Range
15: 0
Default &
Access
8086h
RO
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Description
Vendor ID (value): PCI Vendor ID for Intel
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17.5.2
Device ID (DEVICE_ID)—Offset 2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
DEVICE_ID: [B:0, D:20, F:0] + 2h
Default: 08A7h
15
0
0
0
8
1
0
0
4
0
1
0
1
0
0
0
1
1
1
value
0
12
Bit
Range
Default &
Access
08A7h
RO
15: 0
17.5.3
Description
Device ID (value): PCI Device ID
Command Register (COMMAND_REGISTER)—Offset 4h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
COMMAND_REGISTER: [B:0, D:20, F:0] + 4h
Default: 0000h
0
0
0
0
0
0
0
0
0
RSVD
0
MEMen
0
0
MasEn
0
4
RSVD
0
SERREn
0
8
RSVD
0
RSVD0
0
12
IntrDis
15
Bit
Range
Default &
Access
15: 11
0h
RO
RSVD0 (RSVD0): Reserved
10
0b
RW
Interrupt Disable (IntrDis): Interrupt disable. Disables generation of interrupt
messages in the PCI Express function. 1 =) disabled, 0 =) not disabled
9
0h
RO
Reserved (RSVD): Reserved.
8
0b
RW
SERR Enable (SERREn): When set, this bit enables the non-fatal and fatal errors
detected by the function to be reported to the root complex.
7: 3
00h
RO
Reserved (RSVD): Reserved.
2
0b
RW
Bus Master Enable (MasEn): 0=)disables upstream requests 1=)enables upstream
requests.
1
0b
RW
Memory Space Enable (MEMen): Device support for Memory transactions. 0 =) not
supported. 1 =) supported.
0
0h
RO
Reserved (RSVD): Reserved.
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Description
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17.5.4
Status Register (STATUS)—Offset 6h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
STATUS: [B:0, D:20, F:0] + 6h
Default: 0010h
Bit
Range
17.5.5
Default &
Access
0
1
0
0
0
0
RSVD1
0
0
IntrStatus
0
hasCapList
0
capable_66Mhz
0
RSVD
0
FastB2B
0
4
RSVD
0
DEVSEL
0
8
RSVD
0
RcdMasAb
0
SigSysErr
12
RSVD0
15
Description
15
0h
RO
RSVD0 (RSVD0): Reserved
14
0b
RW
Signaled System Error (SigSysErr): Set when a function detects a system error and
the SERR Enable bit is set
13
0b
RW
Received master abort (RcdMasAb): Set when requester receives a completion with
Unsupported Request completion status
12: 11
0h
RO
Reserved (RSVD): Reserved.
10: 9
0b
RO
DEVSEL Timing (DEVSEL): Deprecated: Hardwired to 0
8
0h
RO
Reserved (RSVD): Reserved.
7
0b
RO
Fast Back-to-Back Capable (FastB2B): Deprecated: Hardwired to 0
6
0h
RO
Reserved (RSVD): Reserved.
5
0b
RO
66MHz-Capable (capable_66Mhz): Deprecated: Hardwired to 0
4
1h
RO
Capabilities List (hasCapList): Indicates the presence of one or more capability
register sets.
3
0b
RO
Interrupt Status (IntrStatus): Indicates that the function has a legacy interrupt
request outstanding. This bit has no meaning if Message Signaled Interrupts are being
used
2: 0
0h
RO
RSVD1 (RSVD1): Reserved
Revision ID and Class Code (REV_ID_CLASS_CODE)—Offset 8h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
REV_ID_CLASS_CODE: [B:0, D:20, F:0] + 8h
Default: 08050110h
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0
0
1
0
0
0
20
0
0
0
17.5.6
0
1
0
1
12
0
0
0
subClassCode
0
16
0
8
0
0
0
1
4
0
0
0
1
0
0
0
0
0
rev_id
0
24
classCode
0
28
progIntf
31
Bit
Range
Default &
Access
31: 24
08h
RO
Class Code (classCode): Broadly classifies the type of function that the device
performs.
23: 16
05h
RO
Sub-Class Code (subClassCode): Identifies more specifically (than the class_code
byte) the function of the device.
15: 8
01h
RO
Programming Interface (progIntf): Used to define the register set variation within a
particular sub-class.
7: 0
10h
RO
Revision ID (rev_id): Assigned by the function manufacturer and identifies the
revision number of the function.
Description
Cache Line Size (CACHE_LINE_SIZE)—Offset Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
CACHE_LINE_SIZE: [B:0, D:20, F:0] + Ch
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
17.5.7
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Cache Line Size (value): Implemented as a R/W register for legacy purposes but has
no effect on device functionality.
Latency Timer (LATENCY_TIMER)—Offset Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
LATENCY_TIMER: [B:0, D:20, F:0] + Dh
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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17.5.8
Bit
Range
Default &
Access
7: 0
0h
RO
Description
Latency Timer (value): Deprecated. Hardwire to 0.
Header Type (HEADER_TYPE)—Offset Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
HEADER_TYPE: [B:0, D:20, F:0] + Eh
Default: 80h
7
4
0
0
0
multiFnDev
Bit
Range
17.5.9
0
0
0
0
0
cfgHdrFormat
1
Default &
Access
Description
7
1h
RO
Multi-Function Device (multiFnDev): Hard-wired to 1 to indicate that this is a multifunction device
6: 0
0h
RO
Configuration Header Format (cfgHdrFormat): Hard-wired to 0 to indicate that this
configuration header is a Type 0 header, i.e. it is an endpoint rather than a bridge.
BIST (BIST)—Offset Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
BIST: [B:0, D:20, F:0] + Fh
Default: 00h
7
4
0
0
Default &
Access
0
0
Description
7
0h
RO
BIST_capable (BIST_capable): Hard-wired to 0. (Returns 1 if the function
implements a BIST)
6
0h
RO
Start (start_bist): Set to start the functions BIST if BIST is supported.
5: 4
0h
RO
Reserved (RSVD): Reserved.
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0
comp_code
BIST_capable
Bit
Range
0
RSVD
0
start_bist
0
0
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17.5.10
Bit
Range
Default &
Access
3: 0
0h
RO
Description
Completion Code (comp_code): Completion code having run BIST if BIST is
supported. 0=)success. non-zero=)failure
Base Address Register (BAR0)—Offset 10h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
BAR0: [B:0, D:20, F:0] + 10h
Default: 00000000h
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
17.5.11
0
4
0
0
0
0
0
0
0
0
0
isIO
0
memType
0
prefetchable
28
0
address
0
RSVD
31
Bit
Range
Default &
Access
Description
31: 12
0h
RW
address (address): Used to determine the size of memory required by the device and
to assign a start address for this required amount of memory.
11: 4
00h
RO
Reserved (RSVD): Reserved.
3
0b
RO
Prefetchable (prefetchable): Defines the block of memory as prefetchable or not. A
block of memory is prefetchable if it fulfils the following 3 conditions (1) no side effects
on reads, (2) the device returns all bytes on reads regardless of the byte enables, and
(3) host bridges can merge processor writes into this range without causing errors.
Hardwired to 0
2: 1
00b
RO
Type (memType): Hardwired to 0 to indicate a 32-bit decoder
0
0b
RO
Memory Space Indicator (isIO): Hardwired to 0 to indicate the register is a memory
address decoder
Cardbus CIS Pointer (CARDBUS_CIS_POINTER)—Offset 28h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CARDBUS_CIS_POINTER: [B:0, D:20, F:0] + 28h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
value
0
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Bit
Range
Default &
Access
0h
RO
31: 0
17.5.12
Description
Cardbus CIS Pointer (value): Reserved. Hardwire to 0.
Subsystem Vendor ID (SUB_SYS_VENDOR_ID)—Offset 2Ch
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_VENDOR_ID: [B:0, D:20, F:0] + 2Ch
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
0h
RO
15: 0
17.5.13
Description
Subsystem Vendor ID (value): PCI Subsystem Vendor ID
Subsystem ID (SUB_SYS_ID)—Offset 2Eh
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
SUB_SYS_ID: [B:0, D:20, F:0] + 2Eh
Default: 0000h
15
12
0
0
0
8
0
0
0
4
0
0
0
0
0
0
value
0
Bit
Range
15: 0
17.5.14
Default &
Access
0h
RO
Description
Subsystem ID (value): PCI Subsystem ID
Expansion ROM Base Address (EXP_ROM_BASE_ADR)—Offset
30h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
EXP_ROM_BASE_ADR: [B:0, D:20, F:0] + 30h
Default: 00000000h
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0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
17.5.15
0
0
0
0
0
0
0
0
AddrDecodeEn
0
24
ROM_base_addr
0
28
RSVD
31
Bit
Range
Default &
Access
Description
31: 11
0h
RW
ROM Start Address (ROM_base_addr): Used to determine the size of memory
required by the ROM and to assign a start address for this required amount of memory.
10: 1
000h
RO
0
0h
RW
Reserved (RSVD): Reserved.
Address Decode Enable (AddrDecodeEn): A 1 in this field enables the function's
ROM address decoder assuming that the Memory Space bit in the Command Register is
also set to 1
Capabilities Pointer (CAP_POINTER)—Offset 34h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
CAP_POINTER: [B:0, D:20, F:0] + 34h
Default: 00000080h
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
1
0
0
RSVD0
0
Bit
Range
17.5.16
0
0
0
0
0
0
value
31
Default &
Access
Description
31: 8
0h
RO
RSVD0 (RSVD0): Reserved
7: 0
80h
RO
Capabilities Pointer (value): Pointer to memory location of first entry of linked list of
configuration register sets each of which supports a feature. Points to PM (power
management) register set at location 0x80
Interrupt Line Register (INTR_LINE)—Offset 3Ch
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_LINE: [B:0, D:20, F:0] + 3Ch
Default: 00h
7
0
0
0
0
0
0
0
0
value
0
4
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.5.17
Bit
Range
Default &
Access
Description
7: 0
0h
RW
Interrupt Line Register (value): The value in this register tells which input of the
system interrupt controller(s) the device's interrupt pin is connected to. The device itself
does not use this value, rather it is used by device drivers and operating systems.
Device drivers and operating systems can use this information to determine priority and
vector information.
Interrupt Pin Register (INTR_PIN)—Offset 3Dh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
INTR_PIN: [B:0, D:20, F:0] + 3Dh
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
17.5.18
Bit
Range
Default &
Access
Description
7: 0
01h
RO
Interrupt Pin Register (value): The Interrupt Pin register tells which interrupt pin the
device (or device function) uses. A value of 1 corresponds to INTA#. A value of 2
corresponds to INTB#. A value of 3 corresponds to INTC#. A value of 4 corresponds to
INTD#. Devices (or device functions) that do not use an interrupt pin must put a 0 in
this register. The values 05h through FFh are reserved. For this system function 0 is
connected to INTA, 1 to INTB, 2 to INTC 3 to INTD, 4 to INTA, 5 to INTB etc.
MIN_GNT (MIN_GNT)—Offset 3Eh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MIN_GNT: [B:0, D:20, F:0] + 3Eh
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
17.5.19
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MIN_GNT (value): Hardwired to 0
MAX_LAT (MAX_LAT)—Offset 3Fh
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MAX_LAT: [B:0, D:20, F:0] + 3Fh
Default: 00h
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7
4
0
0
0
0
0
0
0
0
1
value
0
0
17.5.20
Bit
Range
Default &
Access
7: 0
0h
RO
Description
MAX_LAT (value): Hardwired to 0
Capability ID (PM_CAP_ID)—Offset 80h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_CAP_ID: [B:0, D:20, F:0] + 80h
Default: 01h
7
4
0
0
0
0
0
0
value
0
17.5.21
Bit
Range
Default &
Access
7: 0
01h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (PM_NXT_CAP_PTR)—Offset 81h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PM_NXT_CAP_PTR: [B:0, D:20, F:0] + 81h
Default: A0h
7
4
0
1
0
0
0
0
0
0
value
1
17.5.22
Bit
Range
Default &
Access
7: 0
a0h
RO
Description
Next Capability Pointer (value): Pointer to the next register set of feature specific
configuration registers. Hardwired to 0xA0 to point to the MSI Capability Structure
Power Management Capabilities (PMC)—Offset 82h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
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606
PMC: [B:0, D:20, F:0] + 82h
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Default: 4803h
17.5.23
0
4
0
0
0
0
0
0
0
1
1
version
0
PME_clock
0
RSVD
8
1
DSI
0
aux_curr
0
D1_support
12
1
PME_support
0
D2_support
15
Bit
Range
Default &
Access
Description
15: 11
09h
RO
PME Support (PME_support): PME_Support field Indicates the PM states within which
the function is capable of sending a PME (Power Management Event) message. 0 in a bit
=) PME is not supported in the corresponding PM state, where bit indexes
11,12,13,14,15 correspond to PM states D0, D1, D2, D3hot, D3cold respectively.
10
0h
RO
D2 Support (D2_support): Hardwired to 0 as the D2 state is not supported
9
0h
RO
D1 Support (D1_support): Hardwired to 0 as the D1 state is not supported
8: 6
0h
RO
Aux Current (aux_curr): Hardwired to 0 as the D3hot state is not supported
5
0h
RO
Device Specific Initialisation (DSI): Hardwired to 0 to indicate that the device does
not require a device specific initialisation sequence following transition to the D0
uninitialised state
4
0h
RO
Reserved (RSVD): Reserved.
3
0h
RO
PME Clock (PME_clock): Deprecated. Hardwired to 0
2: 0
011b
RO
Version (version): This function complies with revision 1.2 of the PCI Power
Management Interface Specification
Power Management Control/Status Register (PMCSR)—Offset
84h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
PMCSR: [B:0, D:20, F:0] + 84h
Default: 0008h
0
0
0
0
0
0
0
0
0
0
1
0
RSVD
0
4
0
0
0h
RW
PME Status (PME_status): Set if function has experienced a PME (even if PME_en (bit
8 of PMCSR register) is not set).
0h
RO
Data Scale (Data_scale): Hardwired to 0 as the data register is not supported
15
14: 13
August 2015
Document Number: 329676-005US
power_state
Description
RSVD
Default &
Access
PME_en
Bit
Range
Data_select
Data_scale
0
8
PME_status
0
12
no_soft_reset
15
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Datasheet
607
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
17.5.24
Default &
Access
Description
12: 9
0h
RO
Data Select (Data_select): Hardwired to 0 as the data register is not supported
8
0b
RW
PME Enable (PME_en): Enable device function to send PME messages when an event
occurs. 1=)enabled. 0=)disabled
7: 4
0h
RO
Reserved (RSVD): Reserved.
3
1b
RO
No Soft Reset (no_soft_reset): Devices do perform an internal reset when
transitioning from D3hot to D0
2
0h
RO
Reserved (RSVD): Reserved.
1: 0
00b
RW
Power State (power_state): Allows software to read current PM state or transition
device to a new PM state, where 2'b00 = D0, 2'b01=D1, 2'b10=D2, 2'b11=D3hot
PM CSR PCI-to-PCI Bridge Support Extension (PMCSR_BSE)—
Offset 86h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
PMCSR_BSE: [B:0, D:20, F:0] + 86h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
17.5.25
Bit
Range
Default &
Access
7: 0
0h
RO
Description
PM CSR PCI-to-PCI Bridge Support Extension (value): Not Supported. Hardwired
to 0.
Power Management Data Register (DATA_REGISTER)—Offset
87h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
DATA_REGISTER: [B:0, D:20, F:0] + 87h
Default: 00h
7
4
0
0
0
0
0
0
0
0
value
0
Bit
Range
Default &
Access
7: 0
0h
RO
Intel® Quark™ SoC X1000
Datasheet
608
Description
Power Management Data Register (value): Not Supported. Hardwired to 0
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.5.26
Capability ID (MSI_CAP_ID)—Offset A0h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_CAP_ID: [B:0, D:20, F:0] + A0h
Default: 05h
7
4
0
0
0
0
1
0
1
value
0
0
17.5.27
Bit
Range
Default &
Access
7: 0
05h
RO
Description
Capability ID (value): Identifies the feature associated with this register set.
Hardwired value as per PCI SIG assigned capability ID
Next Capability Pointer (MSI_NXT_CAP_PTR)—Offset A1h
Access Method
Type: PCI Configuration Register
(Size: 8 bits)
MSI_NXT_CAP_PTR: [B:0, D:20, F:0] + A1h
Default: 00h
7
4
0
0
0
0
0
0
0
value
0
0
17.5.28
Bit
Range
Default &
Access
Description
7: 0
00h
RO
Next Capability Pointer (value): Hardwired to 0 as this is the last capability structure
in the chain
Message Control (MESSAGE_CTRL)—Offset A2h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_CTRL: [B:0, D:20, F:0] + A2h
Default: 0100h
August 2015
Document Number: 329676-005US
0
0
1
0
0
0
0
0
0
0
0
MSIEnable
0
0
multiMsgCap
0
4
multiMsgEn
0
8
bit64Cap
0
RSVD0
0
12
perVecMskCap
15
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
17.5.29
Default &
Access
Description
15: 9
0h
RO
RSVD0 (RSVD0): Reserved
8
1h
RO
Per Vector Masking Capable (perVecMskCap): Hardwired to 1 to indicate the
function supports PVM
7
0h
RO
64 bit Address Capabale (bit64Cap): This bit is hardwired to 0 to indicate that the
function is not capable of sending a 64-bit message address.
6: 4
0h
RW
Multi-Message Enable (multiMsgEn): As only one vector is supported per function,
software should only write a value of 0x0 to this field
3: 1
0h
RO
Multiple Message Enable (multiMsgCap): This field is hardwired to 0x0 to indicate
that the function is requesting a single vector
0
0h
RW
MSI Enable (MSIEnable): Set to enable MSI to request service. If set then it's
prohibited to use the INTx pin. System configuration software sets this bit to enable
MSI.
Message Address (MESSAGE_ADDR)—Offset A4h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
MESSAGE_ADDR: [B:0, D:20, F:0] + A4h
Default: 00000000h
31
28
0
0
0
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
Bit
Range
17.5.30
0
0
RSVD0
address
0
24
Default &
Access
Description
31: 2
0h
RW
Message Address (address): If the Message Enable bit (bit 0 of the Message Control
register) is set, the contents of this register specify the DWORD-aligned address
(AD[31:2]) for the MSI memory write transaction. AD[1:0] are driven to zero during the
address phase. This field is read/write
1: 0
0h
RO
RSVD0 (RSVD0): Reserved
Message Data (MESSAGE_DATA)—Offset A8h
Access Method
Type: PCI Configuration Register
(Size: 16 bits)
MESSAGE_DATA: [B:0, D:20, F:0] + A8h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
MsgData
0
12
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
0h
RW
Data Field (MsgData): System-specified message data. If the Message Enable bit (bit
0 of the Message Control register) is set, the message data is driven onto the lower
word (AD[15:0]) of the memory write transactions data phase. AD[31:16] are driven to
zero during the memory write transactions data phase. C/BE[3::0]# are asserted during
the data phase of the memory write transaction. None of the message bits will be
changed by hardware
15: 0
17.5.31
Mask Bits for MSI (PER_VEC_MASK)—Offset ACh
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_MASK: [B:0, D:20, F:0] + ACh
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
Bit
Range
17.5.32
0
MSIMask
RSVD0
0
28
Default &
Access
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RW
Vector 0 Mask (MSIMask): Mask Bit for Vector 0. If this bit is set, the function will not
send MSI messages
Pending Bits for MSI (PER_VEC_PEND)—Offset B0h
Access Method
Type: PCI Configuration Register
(Size: 32 bits)
PER_VEC_PEND: [B:0, D:20, F:0] + B0h
Default: 00000000h
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
RSVD0
0
28
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
0
Description
31: 1
0h
RO
RSVD0 (RSVD0): Reserved
0
0h
RO
Vector 0 Pending (value): Pending Bit for Vector 0.
August 2015
Document Number: 329676-005US
0
4
value
31
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17.6
Memory Mapped Registers
Table 112.
Summary of Memory Mapped I/O Registers—BAR0
Offset Start
Offset End
Default
Value
Register ID—Description
0h
3h
“SDMA System Address Register (SYS_ADR)—Offset 0h” on page 613
00000000h
4h
5h
“Block Size Register (BLK_SIZE)—Offset 4h” on page 614
0000h
6h
7h
“Block Count Register (BLK_COUNT)—Offset 6h” on page 615
0000h
8h
Bh
“Argument Register (ARGUMENT)—Offset 8h” on page 616
00000000h
Ch
Dh
“Transfer Mode Register (TX_MODE)—Offset Ch” on page 616
0000h
Eh
Fh
“Command Register (CMD)—Offset Eh” on page 618
0000h
10h
13h
“Response Register 0 (RESPONSE0)—Offset 10h” on page 619
00000000h
14h
17h
“Response Register 2 (RESPONSE2)—Offset 14h” on page 620
00000000h
18h
1Bh
“Response Register 4 (RESPONSE4)—Offset 18h” on page 620
00000000h
1Ch
1Fh
“Response Register 6 (RESPONSE6)—Offset 1Ch” on page 621
00000000h
20h
23h
“Buffer Data Port Register (BUF_DATA_PORT)—Offset 20h” on page 621
00000000h
24h
27h
“Present State Register (PRE_STATE)—Offset 24h” on page 622
1FF00000h
28h
28h
“Host Control Register (HOST_CTL)—Offset 28h” on page 627
00h
29h
29h
“Power Control Register (PWR_CTL)—Offset 29h” on page 628
00h
2Ah
2Ah
“Block Gap Control Register (BLK_GAP_CTL)—Offset 2Ah” on page 628
00h
2Ch
2Dh
“Clock Control Register (CLK_CTL)—Offset 2Ch” on page 630
0000h
2Eh
2Eh
“Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh” on page 632
00h
2Fh
2Fh
“Software Reset Register (SW_RST)—Offset 2Fh” on page 633
00h
30h
31h
“Normal Interrupt Status Register (NML_INT_STATUS)—Offset 30h” on page 634
0000h
32h
33h
“Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h” on page 636
0000h
34h
35h
“Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—Offset 34h” on
page 638
0000h
36h
37h
“Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—Offset 36h” on
page 639
0000h
38h
39h
“Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—Offset 38h” on
page 640
0000h
3Ah
3Bh
“Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—Offset 3Ah” on
page 642
0000h
3Ch
3Dh
“Auto CMD12 Error Status Register (CMD12_ERR_STAT)—Offset 3Ch” on page 643 0000h
3Eh
3Fh
“Host Control 2 Register (HOST_CTRL_2)—Offset 3Eh” on page 644
0000h
40h
43h
“Capabilities Register (CAPABILITIES)—Offset 40h” on page 645
01EC32B2h
44h
47h
“Capabilities Register 2 (CAPABILITIES_2)—Offset 44h” on page 647
03000000h
48h
4Bh
“Maximum Current Capabilities Register (MAX_CUR_CAP)—Offset 48h” on
page 648
00000001h
50h
51h
“Force Event Register for Auto CMD12 Error Status
(FORCE_EVENT_CMD12_ERR_STAT)—Offset 50h” on page 649
0000h
52h
53h
“Force Event Register for Error Interrupt Status (FORCE_EVENT_ERR_INT_STAT)—
0000h
Offset 52h” on page 650
54h
54h
“ADMA Error Status Register (ADMA_ERR_STAT)—Offset 54h” on page 651
00h
58h
5Bh
“ADMA System Address Register (ADMA_SYS_ADDR)—Offset 58h” on page 652
00000000h
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Table 112.
Offset Start
Summary of Memory Mapped I/O Registers—BAR0 (Continued)
Offset End
Default
Value
Register ID—Description
60h
61h
“initialization Preset Values Register (3.3v or 1.8v) (PRESET_VALUE_0)—Offset
60h” on page 653
0040h
62h
63h
“Default Speed Preset Values Register (PRESET_VALUE_1)—Offset 62h” on
page 653
0001h
64h
65h
“High Speed Preset Values Register (PRESET_VALUE_2)—Offset 64h” on page 654 0000h
66h
67h
“SDR12 Preset Values Register (PRESET_VALUE_3)—Offset 66h” on page 654
0001h
68h
69h
“SDR25 Preset Values Register (PRESET_VALUE_4)—Offset 68h” on page 655
0000h
6Ah
6Bh
“SDR50 Preset Values Register (PRESET_VALUE_5)—Offset 6Ah” on page 656
0000h
6Ch
6Dh
“SDR104 Preset Values Register (PRESET_VALUE_6)—Offset 6Ch” on page 656
0000h
6Eh
6Fh
“DDR50 Preset Values Register (PRESET_VALUE_7)—Offset 6Eh” on page 657
0000h
70h
73h
“Boot Time-out control register (BOOT_TIMEOUT_CTRL)—Offset 70h” on page 658 00000000h
74h
74h
“Debug Selection Register (DEBUG_SEL)—Offset 74h” on page 658
00h
E0h
E3h
“Shared Bus Control Register (SHARED_BUS)—Offset E0h” on page 659
00000000h
F0h
F0h
“SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h” on page 660
00h
FCh
FDh
“Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh” on page 661
0000h
FEh
FFh
“Host Controller Version Register (HOST_CTRL_VER)—Offset FEh” on page 661
A702h
17.6.1
SDMA System Address Register (SYS_ADR)—Offset 0h
This register contains the physical system memory address used for DMA transfers or
the second argument for the Auto CMD23
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
SYS_ADR: [BAR0] + 0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
sys_adr
0
28
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Bit
Range
31: 0
17.6.2
Default &
Access
Description
0h
RW
SDMA System Address / Auto CMD23 Argument 2 (sys_adr): This register
contains the physical system memory address used for DMA transfers (1) or the second
argument for the Auto CMD23 (2).
(1) SDMA System Address This register contains the system memory address for a
SDMA transfer. When the Host Controller stops a SDMA transfer, this register shall point
to the system address of the next contiguous data position. It can be accessed only if no
transaction is executing (i.e., after a transaction has stopped). Read operations during
transfers may return an invalid value. The Host Driver shall initialize this register before
starting a SDMA transaction. After SDMA has stopped, the next system address of the
next contiguous data position can be read from this register. The SDMA transfer waits at
the every boundary specified by the Host SDMA Buffer Boundary in the Block Size
register. The Host Controller generates DMA Interrupt to request the Host Driver to
update this register. The Host Driver sets the next system address of the next data
position to this register. When the most upper byte of this register (003h) is written, the
Host Controller restarts the SDMA transfer. When restarting SDMA by the Resume
command or by setting Continue Request in the Block Gap Control register, the Host
Controller shall start at the next contiguous address stored here in the SDMA System
Address register. ADMA does not use this register
(2) Argument 2 This register is used with the Auto CMD23 to set a 32-bit block count
value to the argument of the CMD23 while executing Auto CMD23. If Auto CMD23 is
used with ADMA, the full 32-bit block count value can be used. If Auto CMD23 is used
without AMDA, the available block count value is limited by the Block Count register.
65535 blocks is the maximum value in this case.
Block Size Register (BLK_SIZE)—Offset 4h
This register is used to configure the number of bytes in a data block.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
BLK_SIZE: [BAR0] + 4h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
15
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Datasheet
614
0
0
boundary
tx_blk_size_12
0
12
Default &
Access
0h
RW
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
tr_blk_size
15
Description
Transfer Block Size [12] (tx_blk_size_12): Transfer Block Size 12th bit. This bit is
added to support 4Kb Data block transfer.
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
14: 12
11: 0
17.6.3
Default &
Access
Description
000b
RW
Host SDMA Buffer Boundary (boundary): The large contiguous memory space may
not be available in the virtual memory system. To perform long SDMA transfer, SDMA
System Address register shall be updated at every system memory boundary during
SDMA transfer. These bits specify the size of contiguous buffer in the system memory.
The SDMA transfer shall wait at the every boundary specified by these fields and the
Host Controller generates the DMA Interrupt to request the Host Driver to update the
SDMA System Address register. At the end of transfer, the Host Controller may issue or
may not issue DMA Interrupt. In particular, DMA Interrupt shall not be issued after
Transfer Complete Interrupt is issued. In case of this register is set to 0 (buffer size =
4K bytes), lower 12-bit of byte address points data in the contiguous buffer and the
upper 20-bit points the location of the buffer in the system memory. The SDMA transfer
stops when the Host Controller detects carry out of the address from bit 11 to 12. These
bits shall be supported when the SDMA Support in the Capabilities register is set to 1
and this function is active when the DMA Enable in the Transfer Mode register is set to 1.
ADMA does not use this register.
000b 4K bytes (Detects A11 carry out)
001b 8K bytes (Detects A12 carry out)
010b 16K Bytes (Detects A13 carry out)
011b 32K Bytes (Detects A14 carry out)
100b 64K bytes (Detects A15 carry out)
101b 128K Bytes (Detects A16 carry out)
110b 256K Bytes (Detects A17 carry out)
111b 512K Bytes (Detects A18 carry out)
000h
RW
Transfer Block Size (tr_blk_size): This register specifies the block size of data
transfers for CMD17, CMD18, CMD24, CMD25, and CMD53. Values ranging from 1 up to
the maximum buffer size can be set. In case of memory, it shall be set up to 512 bytes
(Refer to SD Host Controller Simplified Specification Version 3.00 - Implementation Note
in Section 1.7.2). It can be accessed only if no transaction is executing (i.e., after a
transaction has stopped). Read operations during transfers may return an invalid value,
and write operations shall be ignored.
0800h 2048 Bytes
... ...
0200h 512 Bytes
01FFh 511 Bytes
... ...
0004h 4 Bytes
0003h 3 Bytes
0002h 2 Bytes
0001h 1 Byte
0000h No data transfer
Block Count Register (BLK_COUNT)—Offset 6h
This register is enabled when Block Count Enable in the Transfer Mode register is set to
1 and is valid only for multiple block transfers.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
BLK_COUNT: [BAR0] + 6h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
15
0
0
0
8
0
0
0
4
0
0
0
0
0
0
0
0
0
0
blk_count
0
12
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Datasheet
615
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
Default &
Access
Description
0000h
RW
Blocks Count For Current Transfer (blk_count): The Host Driver shall set this
register to a value between 1 and the maximum block count. The Host Controller
decrements the block count after each block transfer and stops when the count reaches
zero. Setting the block count to 0 results in no data blocks is transferred. This register
should be accessed only when no transaction is executing (i.e., after transactions are
stopped). During data transfer, read operations on this register may return an invalid
value and write operations are ignored. When a suspend command is completed, the
number of blocks yet to be transferred can be determined by reading this register.
Before issuing a resume command, the Host Driver shall restore the previously saved
block count.
FFFFh 65535 blocks
... ...
0002h 2 blocks
0001h 1 block
0000h Stop Count
15: 0
17.6.4
Argument Register (ARGUMENT)—Offset 8h
This register contains the SD Command Argument.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
ARGUMENT: [BAR0] + 8h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
argument
0
28
Bit
Range
31: 0
17.6.5
Default &
Access
0h
RW
Description
Command Argument 1 (argument): The SD Command Argument is specified as
bit39-8 of Command-Format in the SD Physical Layer Specification.
Transfer Mode Register (TX_MODE)—Offset Ch
This register is used to control the operation of data transfers. The Host Driver shall set
this register before issuing a command which transfers data (Refer to Data Present
Select in the Command register), or before issuing a Resume command. The Host
Driver shall save the value of this register when the data transfer is suspended (as a
result of a Suspend command) and restore it before issuing a Resume command. To
prevent data loss, the Host Controller shall implement write protection for this register
during data transactions. Writes to this register shall be ignored when the Command
Inhibit (DAT) in the Present State register is 1.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
TX_MODE: [BAR0] + Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
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Default: 0000h
0
Bit
Range
Default &
Access
15: 7
000h
RO
6
0b
RW
0
4
0
0
0
0
0
0
0
0
0
dma_en
0
blk_count_en
8
0
cmd12_en
0
data_tr_dir
0
blk_sel
12
0
rsvd
0
cmd_comp_ata
15
Description
RSVD (rsvd): Reserved
Command Completion Signal Enable for CE-ATA Device (cmd_comp_ata): 1 Device will send command completion Signal
0 - Device will not send command completion Signal
NOTE: This filed is not part of the SD Host Controller Specification v3.00.
5
0h
RW
Multi / Single Block Select (blk_sel): This bit is set when issuing multiple-block
transfer commands using DAT line. For any other commands, this bit shall be set to 0. If
this bit is 0, it is not necessary to set the Block Count register. (Refer to Table 2-8 on SD
Host Controller Simplified Specification Version 3.00)
1 Multiple Block
0 Single Block
4
0h
RW
Data Transfer Direction Select (data_tr_dir): This bit defines the direction of DAT
line data transfers. The bit is set to 1 by the Host Driver to transfer data from the SD
card to the SD Host Controller and it is set to 0 for all other commands.
1 Read (Card to Host)
0 Write (Host to Card)
00b
RW
Auto CMD Enable (cmd12_en): This field determines use of auto command functions.
00b Auto Command Disabled
01b Auto CMD12 Enable
10b Auto CMD23 Enable
11b Reserved
There are two methods to stop Multiple-block read and write operation.
(1) Auto CMD12 Enable The Host Controller issues CMD12 automatically when last block
transfer is completed. Auto CMD12 error is indicated to the Auto CMD Error Status
register. The Host Driver shall not set this bit if the command does not require CMD12.
In particular, secure commands defined in the Part 3 File Security specification do not
require CMD12.
(2) Auto CMD23 Enable The Host Controller issues a CMD23 automatically before issuing
a command specified in the Command Register. The following conditions are required to
use the Auto CMD23:
- Auto CMD23 Supported
- A memory card that supports CMD23 (SCR[33]=1)
- If DMA is used, it shall be ADMA.
- Only when CMD18 or CMD25 is issued (Note, the Host Controller does not check
command index.)
Auto CMD23 can be used with or without ADMA. By writing the Command register, the
Host Controller issues a CMD23 first and then issues a command specified by the
Command Index in Command register. If response errors of CMD23 are detected, the
second command is not issued. A CMD23 error is indicated in the Auto CMD Error Status
register. 32-bit block count value for CMD23 is set to SDMA System Address / Argument
2 register
0b
RW
Block Count Enable (blk_count_en): This bit is used to enable the Block Count
register, which is only relevant for multiple block transfers. When this bit is 0, the Block
Count register is disabled, which is useful in executing an infinite transfer. (Refer to
Table 2-8 on SD Host Controller Simplified Specification Version 3.00) If ADMA2 data
transfer is more than 65535 blocks, this bit shall be set to 0. In this case, data transfer
length is designated by Descriptor Table.
1 Enable
0 Disable
3: 2
1
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Bit
Range
0
17.6.6
Default &
Access
Description
0b
RW
DMA Enable (dma_en): DMA can be enabled only if it is supported as indicated in the
Capabilities register. One of the DMA modes can be selected by DMA Select in the Host
Control 1 register. If DMA is not supported, this bit is meaningless and shall always read
0. If this bit is set to 1, a DMA operation shall begin when the Host Driver writes to the
upper byte of Command register (00Fh).
1 DMA Data transfer
0 No data transfer or Non DMA data transfer
Command Register (CMD)—Offset Eh
The Host Driver shall check the Command Inhibit (DAT) bit and Command Inhibit
(CMD) bit in the Present State register before writing to this register. Writing to the
upper byte of this register triggers SD command generation. The Host Driver has the
responsibility to write this register because the Host Controller does not protect for
writing when Command Inhibit (CMD) is set.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
CMD: [BAR0] + Eh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
0
0
0
0
0
0
0
0
0
0
resp_type_sel
0
reserved
0
0
cmd_crc_chk_en
0
4
cmd_index_chk_en
0
cmd_index
0
rsvd
0
8
data_pr_sel
12
cmd_type
15
Bit
Range
Default &
Access
15: 14
0h
RO
RSVD (rsvd): Reserved
13: 8
0h
RW
Command Index (cmd_index): These bits shall be set to the command number
(CMD0-63, ACMD0-63) that is specified in bits 45-40 of the Command-Format in the
Physical Layer Specification and SDIO Card Specification
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Bit
Range
7: 6
5
Default &
Access
Description
00b
RW
Command Type (cmd_type): There are three types of special commands: Suspend,
Resume and Abort. These bits shall be set to 00b for all other commands.
(1) Suspend Command If the Suspend command succeeds, the Host Controller shall
assume the SD Bus has been released and that it is possible to issue the next command,
which uses the DAT line. The Host Controller shall de-assert Read Wait for read
transactions and stop checking busy for write transactions. The interrupt cycle shall
start, in 4-bit mode. If the Suspend command fails, the Host Controller shall maintain its
current state, and the Host Driver shall restart the transfer by setting Continue Request
in the Block Gap Control register.
(2) Resume Command The Host Driver re-starts the data transfer by restoring the
registers in the range of 000-00Dh. The Host Controller shall check for busy before
starting write transfers.
(3) Abort Command If this command is set when executing a read transfer, the Host
Controller shall stop reads to the buffer. If this command is set when executing a write
transfer, the Host Controller shall stop driving the DAT line. After issuing the Abort
command, the Host Driver should issue a software reset.
11b Abort CMD12, CMD52 for writing I/O Abort in CCCR
10b Resume CMD52 for writing Function Select in CCCR
01b Suspend CMD52 for writing Bus Suspend in CCCR
00b Normal Other commands
0b
RW
Data Present Select (data_pr_sel): This bit is set to 1 to indicate that data is present
and shall be transferred using the DAT line. It is set to 0 for the following:
(1) Commands using only CMD line (ex. CMD52).
(2) Commands with no data transfer but using busy signal on DAT[0] line (R1b or R5b
ex. CMD38)
(3) Resume command
1 Data Present
0 No Data Present
0b
RW
Command Index Check Enable (cmd_index_chk_en): If this bit is set to 1, the
Host Controller shall check the Index field in the response to see if it has the same value
as the command index. If it is not, it is reported as a Command Index Error. If this bit is
set to 0, the Index field is not checked.
1 Enable
0 Disable
3
0b
RW
Command CRC Check Enable (cmd_crc_chk_en): If this bit is set to 1, the Host
Controller shall check the CRC field in the response. If an error is detected, it is reported
as a Command CRC Error. If this bit is set to 0, the CRC field is not checked. The position
of CRC field is determined according to the length of the response. (Refer to definition in
D01-00 and Table 2-10 in the SD Host Controller Simplified Specification Version 3.00).
1 Enable
0 Disable
2
0h
RO
Reserved (reserved): Reserved
1: 0
0h
RW
Response Type Select (resp_type_sel): 00 No Response
01 Response Length 136
10 Response Length 48
11 Response Length 48 check Busy after response
4
17.6.7
Response Register 0 (RESPONSE0)—Offset 10h
This register is used to store responses from SD cards
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
RESPONSE0: [BAR0] + 10h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
cmd_resp
0
28
Bit
Range
Default &
Access
Description
0h
RO
Command Response (cmd_resp): Section 2.2.7 and Table 2-12 in the SD Host
Controller Simplified Specification Version 3.00 describe the mapping of command
responses from the SD Bus to this register for each response type. In the table, R[]
refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers
to a bit range within the Response register
31: 0
17.6.8
Response Register 2 (RESPONSE2)—Offset 14h
This register is used to store responses from SD cards
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
RESPONSE2: [BAR0] + 14h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
cmd_resp
0
Bit
Range
31: 0
17.6.9
Default &
Access
Description
0h
RO
Command Response (cmd_resp): Section 2.2.7 and Table 2-12 in the SD Host
Controller Simplified Specification Version 3.00 describe the mapping of command
responses from the SD Bus to this register for each response type. In the table, R[]
refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers
to a bit range within the Response register
Response Register 4 (RESPONSE4)—Offset 18h
This register is used to store responses from SD cards
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
RESPONSE4: [BAR0] + 18h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
cmd_resp
0
28
Bit
Range
Default &
Access
Description
0h
RO
Command Response (cmd_resp): Section 2.2.7 and Table 2-12 in the SD Host
Controller Simplified Specification Version 3.00 describe the mapping of command
responses from the SD Bus to this register for each response type. In the table, R[]
refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers
to a bit range within the Response register
31: 0
17.6.10
Response Register 6 (RESPONSE6)—Offset 1Ch
This register is used to store responses from SD cards
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
RESPONSE6: [BAR0] + 1Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
28
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
cmd_resp
0
Bit
Range
31: 0
17.6.11
Default &
Access
Description
0h
RO
Command Response (cmd_resp): Section 2.2.7 and Table 2-12 in the SD Host
Controller Simplified Specification Version 3.00 describe the mapping of command
responses from the SD Bus to this register for each response type. In the table, R[]
refers to a bit range within the response data as transmitted on the SD Bus, REP[] refers
to a bit range within the Response register
Buffer Data Port Register (BUF_DATA_PORT)—Offset 20h
32-bit data port register to access internal buffer
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
BUF_DATA_PORT: [BAR0] + 20h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
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31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
buf_data
0
28
Bit
Range
Default &
Access
Description
0h
RW
Buffer Data (buf_data): The Host Controller buffer can be accessed through this 32bit Data Port register. Refer to section 1.7 in the SD Host Controller Simplified
Specification Version 3.00
31: 0
17.6.12
Present State Register (PRE_STATE)—Offset 24h
This bit indicates whether one of the DAT line on SD bus is in use. The Host Driver can
get status of the Host Controller from this 32-bit read only register
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
PRE_STATE: [BAR0] + 24h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 1FF00000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
cmd_inhibit_cmd
0
cmd_inhibit_dat
0
re_tune_req
0
0
dat_ln_active
0
4
reserved
0
rd_tx_active
1
wr_tx_active
1
buf_rd_en
1
8
buf_wr_en
1
12
reserved1
1
crd_ins
1
crd_st_stable
1
crd_det_pin_lvl
1
16
wr_prot_sw_pin_lvl
1
20
data_ln_sig_lvl
0
24
cmd_ln_sig_lvl
0
reserved2
0
28
dat_sig_lvl
31
Bit
Range
Default &
Access
31: 29
0h
RO
Reserved2 (reserved2): Reserved
Fh
RO
DAT[7:4] Line Signal Level (dat_sig_lvl): This status is used to check DAT line level
to recover from errors, and for debugging.
D28 - DAT[7]
D27 - DAT[6]
D26 - DAT[5]
D25 - DAT[4]
NOTE: This filed is not part of the SD Host Controller Specification v3.00.
1b
RO
CMD Line Signal Level (cmd_ln_sig_lvl): This status is used to check the CMD line
level to recover from errors, and for debugging.
Fh
RO
DAT[3:0] Line Signal Level (data_ln_sig_lvl): This status is used to check the DAT
line level to recover from errors, and for debugging. This is especially useful in detecting
the busy signal level from DAT[0].
D23 - DAT[3]
D22 - DAT[2]
D21 - DAT[1]
D20 - DAT[0]
28: 25
24
23: 20
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Bit
Range
Default &
Access
Description
0b
RO
Write Protect Switch Pin Level (wr_prot_sw_pin_lvl): The Write Protect Switch is
supported for memory and combo cards. This bit reflects the inverse value of the
SD_WP pin.
1 Write enabled (SD_WP=0)
0 Write protected (SD_WP=1)
18
0b
RO
Card Detect Pin Level (crd_det_pin_lvl): This bit reflects the inverse value of the
SD_CD_B pin. Debouncing is not performed on this bit. This bit may be valid when Card
State Stable is set to 1, but it is not guaranteed because of propagation delay. Use of
this bit is limited to testing since it must be debounced by software.
1 Card present (SD_CD_B=0)
0 No card present (SD_CD_B=1)
17
0b
RO
Card State Stable (crd_st_stable): This bit is used for testing. If it is 0, the Card
Detect Pin Level is not stable. If this bit is set to 1, it means the Card Detect Pin Level is
stable. No Card state can be detected by this bit is set to 1 and Card Inserted is set to 0.
The Software Reset For All in the Software Reset register shall not affect this bit.
1 No Card or Inserted (stable)
0 Reset or Debouncing (unstable)
0b
RO
Card Inserted (crd_ins): This bit indicates whether a card has been inserted. The
Host Controller shall debounce this signal so that the Host Driver will not need to wait
for it to stabilize. Changing from 0 to 1 generates a Card Insertion interrupt in the
Normal Interrupt Status register and changing from 1 to 0 generates a Card Removal
interrupt in the Normal Interrupt Status register. The Software Reset For All in the
Software Reset register shall not affect this bit. If a card is removed while its power is on
and its clock is oscillating, the Host Controller shall clear SD Bus Power in the Power
Control register and SD Clock Enable in the Clock Control register. When this bit is
changed from 1 to 0, the Host Controller shall immediately stop driving CMD and
DAT[3:0] (tri-state). In addition, the Host Driver should clear the Host Controller by the
Software Reset For All in Software Reset register. The card detect is active regardless of
the SD Bus Power.
1 Card Inserted
0 Reset or Debouncing or No Card
0h
RO
Reserved1 (reserved1): Reserved
0b
RO
Buffer Read Enable (buf_rd_en): This status is used for non-DMA read transfers. The
Host Controller may implement multiple buffers to transfer data efficiently. This read
only flag indicates that valid data exists in the host side buffer. If this bit is 1, readable
data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data
is read from the buffer. A change of this bit from 0 to 1 occurs when block data is ready
in the buffer and generates the Buffer Read Ready interrupt.
1 Read enable
0 Read disable
0b
RO
Buffer Write Enable (buf_wr_en): This status is used for non-DMA write transfers.
The Host Controller can implement multiple buffers to transfer data efficiently. This read
only flag indicates if space is available for write data. If this bit is 1, data can be written
to the buffer. A change of this bit from 1 to 0 occurs when all the block data is written to
the buffer. A change of this bit from 0 to 1 occurs when top of block data can be written
to the buffer and generates the Buffer Write Ready interrupt. The Host Controller should
neither set Buffer Write Enable nor generate Buffer Write Ready Interrupt after the last
block data is written to the Buffer Data Port Register.
1 Write enable
0 Write disable
0b
RO
Read Transfer Active (rd_tx_active): This status is used for detecting completion of
a read transfer. (Refer to Section 3.12.3 in the SD Host Controller Simplified
Specification Version 3.00) This bit is set to 1 for either of the following conditions:
(1) After the end bit of the read command.
(2) When read operation is restarted by writing a 1 to Continue Request in the Block
Gap Control register.
This bit is cleared to 0 for either of the following conditions:
(1) When the last data block as specified by block length is transferred to the System.
(2) In case of ADMA2, end of read operation is designated by Descriptor Table.
(3) When all valid data blocks in the Host Controller have been transferred to the
System and no current block transfers are being sent as a result of the Stop At Block
Gap Request being set to 1.
A Transfer Complete interrupt is generated when this bit changes to 0.
1 Transferring data
0 No valid data
19
16
15: 12
11
10
9
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Bit
Range
Default &
Access
Description
8
0b
RO
Write Transfer Active (wr_tx_active): This status indicates a write transfer is active.
If this bit is 0, it means no valid write data exists in the Host Controller. (Refer to Section
3.12.4 in the SD Host Controller Simplified Specification Version 3.00) This bit is set in
either of the following cases:
(1) After the end bit of the write command.
(2) When write operation is restarted by writing a 1 to Continue Request in the Block
Gap Control register.
This bit is cleared in either of the following cases:
(1) After getting the CRC status of the last data block as specified by the transfer count
(Single and Multiple) In case of ADMA2, transfer count is designated by Descriptor
Table.
(2) After getting the CRC status of any block where data transmission is about to be
stopped by a Stop At Block Gap Request.
During a write transaction, a Block Gap Event interrupt is generated when this bit is
changed to 0, as the result of the Stop At Block Gap Request being set. This status is
useful for the Host Driver in determining non DAT line commands can be issued during
write busy.
1 Transferring data
0 No valid data
7: 4
0h
RO
Reserved (reserved): Reserved
0b
RO
Re-Tuning Request (re_tune_req): Host Controller may request Host Driver to
execute re-tuning sequence by setting this bit when the data window is shifted by
temperature drift and a tuned sampling point does not have a good margin to receive
correct data. This bit is cleared when a command is issued with setting Execute Tuning
in the Host Control 2 register. Changing of this bit from 0 to 1 generates Re-Tuning
Event. Refer to Normal Interrupt Status registers for more detail. This bit isn't set to 1 if
Sampling Clock Select in the Host Control 2 register is set to 0 (using fixed sampling
clock). Refer to Re-Tuning Modes in the Capabilities register for more detail.
3
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Bit
Range
2
1
0
Default &
Access
Description
0b
RO
DAT Line Active (dat_ln_active): This bit indicates whether one of the DAT line on
SD Bus is in use.
(a) In the case of read transactions
This status indicates whether a read transfer is executing on the SD Bus. Changing this
value from 1 to 0 generates a Block Gap Event interrupt in the Normal Interrupt Status
register, as the result of the Stop At Block Gap Request being set. Refer to Section
3.12.3 for details on timing. This bit shall be set in either of the following cases:
(1) After the end bit of the read command.
(2) When writing a 1 to Continue Request in the Block Gap Control register to restart a
read transfer.
This bit shall be cleared in either of the following cases: (1) When the end bit of the last
data block is sent from the SD Bus to the Host Controller. In case of ADMA2, the last
block is designated by the last transfer of Descriptor Table.
(2) When a read transfer is stopped at the block gap initiated by a Stop At Block Gap
Request.
The Host Controller shall stop read operation at the start of the interrupt cycle of the
next block gap by driving Read Wait or stopping SD clock. If the Read Wait signal is
already driven (due to data buffer cannot receive data), the Host Controller can continue
to stop read operation by driving the Read Wait signal. It is necessary to support Read
Wait in order to use suspend / resume function.
(b) In the case of write transactions
This status indicates that a write transfer is executing on the SD Bus. Changing this
value from 1 to 0 generate a Transfer Complete interrupt in the Normal Interrupt Status
register. Refer to Section 3.12.4 for sequence details. This bit shall be set in either of the
following cases:
(1) After the end bit of the write command.
(2) When writing to 1 to Continue Request in the Block Gap Control register to continue
a write transfer.
This bit shall be cleared in either of the following cases:
(1) When the SD card releases write busy of the last data block. If SD card does not
drive busy signal for 8 SD Clocks, the Host Controller shall consider the card drive -Not
Busy-. In case of ADMA2, the last block is designated by the last transfer of Descriptor
Table.
(2) When the SD card releases write busy prior to waiting for write transfer as a result of
a Stop At Block Gap Request.
(c) Command with busy
This status indicates whether a command indicates busy (ex. erase command for
memory) is executing on the SD Bus. This bit is set after the end bit of the command
with busy and cleared when busy is de-asserted. Changing this bit from 1 to 0 generate
a Transfer Complete interrupt in the Normal Interrupt Status register. Refer Figure 2-11
to Figure 2-13 on SD Host Controller Simplified Specification Version 3.00.
1 DAT Line Active
0 DAT Line Inactive
0b
RO
Command Inhibit (DAT) (cmd_inhibit_dat): This status bit is generated if either the
DAT Line Active or the Read Transfer Active is set to 1. If this bit is 0, it indicates the
Host Controller can issue the next SD Command. Commands with busy signal belong to
Command Inhibit (DAT) (ex. R1b, R5b type). Changing from 1 to 0 generates a Transfer
Complete interrupt in the Normal Interrupt Status register. Note: The SD Host Driver
can save registers in the range of 000-00Dh for a suspend transaction after this bit has
changed from 1 to 0.
1 Cannot issue command which uses the DAT line
0 Can issue command which uses the DAT line
0b
RO
Command Inhibit (CMD) (cmd_inhibit_cmd): If this bit is 0, it indicates the CMD
line is not in use and the Host Controller can issue a SD Command using the CMD line.
This bit is set immediately after the Command register (00Fh) is written. This bit is
cleared when the command response is received. Auto CMD12 and Auto CMD23 consist
of two responses. In this case, this bit is not cleared by the response of CMD12 or
CMD23 but cleared by the response of a read/write command. Status issuing Auto
CMD12 is not read from this bit. So if a command is issued during Auto CMD12
operation, Host Controller shall manage to issue two commands: CMD12 and a
command set by Command register. Even if the Command Inhibit (DAT) is set to 1,
commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0
generates a Command Complete Interrupt in the Normal Interrupt Status register. If the
Host Controller cannot issue the command because of a command conflict error or
because of Command Not Issued By Auto CMD12 Error (Refer to Section (Refer to
Section 2.2.18 and 2.2.23 SD Host Controller Simplified Specification Version 3.00), this
bit shall remain 1 and the Command Complete is not set.
1 Cannot issue command
0 Can issue command using only CMD line
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17.6.13
Host Control Register (HOST_CTL)—Offset 28h
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
HOST_CTL: [BAR0] + 28h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
0
0
0
led_ctl
0
data_tx_wid
0
hi_spd_en
0
0
dma_sel
crd_det_sig_sel
0
Bit
Range
0
sd8_bit_mode
4
crd_det_tst_lvl
7
Default &
Access
Description
7
0b
RW
Card Detect Signal Selection (crd_det_sig_sel): This bit selects source for the card
detection. When the source for the card detection is switched, the interrupt should be
disabled during the switching period by clearing the Interrupt Status/Signal Enable
register in order to mask unexpected interrupt being caused by the glitch. The Interrupt
Status/Signal Enable should be disabled during over the period of debouncing.
1 The Card Detect Test Level is selected (for test purpose)
0 SD_CD_B is selected (for normal use)
6
0h
RW
Card Detect Test Level (crd_det_tst_lvl): This bit is enabled while the Card Detect
Signal Selection is set to 1 and it indicates card inserted or not. Generates (card ins or
card removal) interrupt when the normal int sts enable bit is set.
1 - Card Inserted
0 - No Card
0h
RW
Extended Data Transfer Width (sd8_bit_mode): This bit controls 8-bit bus width
mode for embedded device. Support of this function is indicated in 8-bit Support for
Embedded Device in the Capabilities register. If a device supports 8-bit bus mode, this
bit may be set to 1. If this bit is 0, bus width is controlled by Data Transfer Width in the
Host Control 1 register. This bit is not effective when multiple devices are installed on a
bus slot (Slot Type is set to 10b in the Capabilities register). In this case, each device
bus width is controlled by Bus Width Preset field in the Shared Bus Control register.
1 8-bit Bus Width
0 Bus Width is Selected by Data Transfer Width
00b
RW
DMA Select (dma_sel): One of supported DMA modes can be selected. The host driver
shall check support of DMA modes by referring the Capabilities register.
00 - SDMA is selected
01 - 32-bit Address ADMA1 is selected
10 - 32-bit Address ADMA2 is selected
11 - 64-bit Address ADMA2 is selected
NOTE: Codes 01 and 11 are not part of the SD Host Controller Simplified Specification
Version 3.00
2
0b
RW
High Speed Enable (hi_spd_en): This bit is optional. Before setting this bit, the HD
shall check the High Speed Support in the capabilities register. If this bit is set to 0
(default), the HC outputs CMD line and DAT lines at the falling edge of the SD clock (up
to 25 MHz/ 20MHz for MMC). If this bit is set to 1, the HC outputs CMD line and DAT
lines at the rising edge of the SD clock (up to 50 MHz for SD/52MHz for MMC)/ 208Mhz
(for SD3.0) If Preset Value Enable in the Host Control 2 register is set to 1, Host Driver
needs to reset SD Clock Enable before changing this field to avoid generating clock
glitches. After setting this field, the Host Driver sets SD Clock Enable again
1 - High Speed Mode
0 - Normal Speed Mode
1
0h
RW
Data Transfer Width (SD1 or SD4) (data_tx_wid): This bit selects the data width of
the Host Controller. The Host Driver shall set it to match the data width of the SD card.
1 4-bit mode
0 1-bit mode
5
4: 3
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Bit
Range
0
17.6.14
Default &
Access
Description
0h
RW
LED Control (led_ctl): This bit is used to caution the user not to remove the card while
the SD card is being accessed. If the software is going to issue multiple SD commands,
this bit can be set during all these transactions. It is not necessary to change for each
transaction.
1 LED on
0 LED off
Power Control Register (PWR_CTL)—Offset 29h
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
PWR_CTL: [BAR0] + 29h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
4
0
0
0
0
hw_rst
0
Bit
Range
Default &
Access
7: 5
0h
RO
RSVD (rsvd): Reserved
4
0b
RW
HW reset (hw_rst): Hardware reset signal is generated for eMMC4.4 card when this
bit is set.
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
0h
RW
SD Bus Voltage Select (sd_bus_volt_sel): By setting these bits, the Host Driver
selects the voltage level for the SD card. Before setting this register, the Host Driver
shall check the Voltage Support bits in the Capabilities register. If an unsupported
voltage is selected, the Host System shall not supply SD Bus voltage.
111 3.3V (Typ.)
110 Reserved
101 Reserved
0b
RW
SD Bus Power (sd_bus_pwr): Before setting this bit, the SD Host Driver shall set SD
Bus Voltage Select. If the Host Controller detects the No Card state, this bit shall be
cleared. If this bit is cleared, the Host Controller shall immediately stop driving CMD and
DAT[3:0] (tri-state) and drive SDCLK to low level (Refer to Section 2.2.14 of SD Host
Controller Simplified Specification Version 3.00).
1 Power on
0 Power off
3: 1
0
17.6.15
0
sd_bus_pwr
0
rsvd
0
0
sd_bus_volt_sel
7
Description
Block Gap Control Register (BLK_GAP_CTL)—Offset 2Ah
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
BLK_GAP_CTL: [BAR0] + 2Ah
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Default: 00h
0
0
0
0
0
spi_mode
int_blk_gap
rd_wait_ctl
cont_req
stp_blk_gap_req
rsvd
Bit
Range
0
0
boot_en
4
0
alt_boot_en
7
0
Default &
Access
Description
7
0b
RO
RSVD (rsvd): Reserved
6
0b
RW
Alternate Boot Mode Enable (alt_boot_en): To start boot code access in alternative
mode.
1 - To start alternate boot mode access
0 - To stop alternate boot mode access
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
5
0b
RW
Boot Enable (boot_en): To start boot code access
1 - To start boot code access
0 - To stop boot code access
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
4
0b
RW
SPI mode enable (spi_mode): SPI mode enable bit.
1 - SPI mode
0 - SD mode
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
0b
RW
Interrupt At Block Gap (int_blk_gap): This bit is valid only in 4-bit mode of the
SDIO card and selects a sample point in the interrupt cycle. Setting to 1 enables
interrupt detection at the block gap for a multiple block transfer. Setting to 0 disables
interrupt detection during a multiple block transfer. If the SD card cannot signal an
interrupt during a multiple block transfer, this bit should be set to 0. When the Host
Driver detects an SD card insertion, it shall set this bit according to the CCCR of the
SDIO card.
1 Enabled
0 Disabled
0b
RW
Read Wait Control (rd_wait_ctl): The read wait function is optional for SDIO cards.
If the card supports read wait, set this bit to enable use of the read wait protocol to stop
read data using the DAT[2] line. Otherwise, the Host Controller has to stop the SD Clock
to hold read data, which restricts commands generation. When the Host Driver detects
an SD card insertion, it shall set this bit according to the CCCR of the SDIO card. If the
card does not support read wait, this bit shall never be set to 1 otherwise DAT line
conflict may occur. If this bit is set to 0, Suspend/Resume cannot be supported.
1 Enable Read Wait Control
0 Disable Read Wait Control
0b
RW
Continue Request (cont_req): This bit is used to restart a transaction, which was
stopped using the Stop At Block Gap Request. To cancel stop at the block gap, set Stop
At Block Gap Request to 0 and set this bit 1 to restart the transfer. The Host Controller
automatically clears this bit in either of the following cases: (1) In the case of a read
transaction, the DAT Line Active changes from 0 to 1 as a read transaction restarts.
(2) In the case of a write transaction, the Write Transfer Active changes from 0 to 1 as
the write transaction restarts.
Therefore, it is not necessary for Host Driver to set this bit to 0. If Stop At Block Gap
Request is set to 1, any write to this bit is ignored.
1 Restart
0 Not affect
3
2
1
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Bit
Range
0
17.6.16
Default &
Access
Description
0b
RW
Stop At Block Gap Request (stp_blk_gap_req): This bit is used to stop executing
read and write transaction at the next block gap for non-DMA, SDMA and ADMA
transfers. The Host Driver shall leave this bit set to 1 until the Transfer Complete is set
to 1. Clearing both Stop At Block Gap Request and Continue Request shall not cause the
transaction to restart. When Host Controller version is 1.00, the Host Driver can set this
bit if the card supports Read Wait Control. When Host Controller version is 2.00 or later,
the Host Driver can set this bit regardless of the card supports Read Wait Control. The
Host Controller shall stop read transfer by using Read Wait or stopping SD clock. In case
of write transfers in which the Host Driver writes data to the Buffer Data Port register,
the Host Driver shall set this bit after all block data is written. If this bit is set to 1, the
Host Driver shall not write data to Buffer Data Port register. This bit affects Read
Transfer Active, Write Transfer Active, DAT Line Active and Command Inhibit (DAT) in
the Present State register.
1 Stop
0 Transfer
Clock Control Register (CLK_CTL)—Offset 2Ch
This register is used configure the frequency of the SDIO controller, and enable the
clock.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
CLK_CTL: [BAR0] + 2Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
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Document Number: 329676-005US
0
0
0
0
0
0
0
0
0
0
int_clk_en
0
int_clk_stable
0
sd_clk_en
0
0
rsvd
0
4
clk_gen_sel
0
8
sdclk_freq_sel
0
12
upr_sdclk_freq_sel
15
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Datasheet
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
Default &
Access
Description
15: 8
00h
RW
SDCLK Frequency Select (sdclk_freq_sel): This register is used to select the
frequency of the SDCLK pin. The frequency is not programmed directly; rather this
register holds the divisor of the Base Clock Frequency For SD clock in the capabilities
register. Only the following settings are allowed.
(1) 8-bit Divided Clock Mode
80h - base clock divided by 256
40h - base clock divided by 128
20h - base clock divided by 64
10h - base clock divided by 32
08h - base clock divided by 16
04h - base clock divided by 8
02h - base clock divided by 4
01h - base clock divided by 2
00h - base clock(10MHz-63MHz)
Setting 00h specifies the highest frequency of the SD Clock. When setting multiple bits,
the most significant bit is used as the divisor. But multiple bits should not be set. The
two default divider values can be calculated by the frequency that is defined by the Base
Clock Frequency For SD Clock in the Capabilities register.
- 400KHz divider value
- 25MHz divider value
- 50MHz divider value
The frequency of the SDCLK is set by the following formula: Clock Frequency = (Base
clock) / divisor. Thus choose the smallest possible divisor which results in a clock
frequency that is less than or equal to the target frequency. Maximum Frequency for SD
= 50Mhz (base clock) Maximum Frequency for MMC = 52Mhz (base clock) Minimum
Frequency = 195.3125Khz (50Mhz / 256), same clock for MMC also.
For example, if the Base Clock Frequency For SD Clock in the Capabilities register has
the value 33MHz, and the target frequency is 25MHz, then choosing the divisor value of
01h will yield 16.5MHz, which is the nearest frequency less than or equal to the target.
Similarly, to approach a clock value of 400KHz, the divisor value of 40h yields the
optimal clock value of 258KHz.
(2) 10-bit Divided Clock Mode
Host Controller Version 3.00 supports this mandatory mode instead of the 8-bit Divided
Clock Mode. The length of divider is extended to10 bits and all divider values shall be
supported.
3FFh 1/2046 Divided Clock
...
N 1/2N Divided Clock (Duty 50%)
...
002h 1/4 Divided Clock
001h 1/2 Divided Clock
000h Base Clock (10MHz-255MHz)
(3) Programmable Clock Mode
Host Controller Version 3.00 supports this mode as optional. A non-zero value set to
Clock Multiplier in the Capabilities register indicates support of this clock mode. The
multiplier enables the Host System to select a finer grain SD clock frequency. It is not
necessary to support all frequency generation specified by this field because
programmable clock generator is vendor specific and dependent on the implementation.
Therefore, this mode is used with Preset Value registers. The Host Controller vendor
provides possible settings and the Host System vendor sets appropriate values to the
Preset Value registers.
3FFh Base Clock * M / 1024
...
N - 1 Base Clock * M / N
...
002h Base Clock * M / 3
001h Base Clock * M / 2
000h Base Clock * M
This field depends on setting of Preset Value Enable in the Host Control 2 register. If
Preset Value Enable = 0, this field is set by Host Driver. If the Preset Value Enable = 1,
this field is automatically set to a value specified in one of Preset Value registers.
7: 6
00b
RW
Upper Bits of SDCLK Frequency Select (upr_sdclk_freq_sel): Host Controller
Version 1.00 and 2.00 do not support these bits and they are treated as 00b fixed value
(ROC). Host Controller Version 3.00 shall support these bits to expand SDCLK
Frequency Select to 10-bit. Bit 07-06 is assigned to bit 09-08 of clock divider in SDCLK
Frequency Select.
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SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
5
0b
RW
Clock Generator Select (clk_gen_sel): This bit is used to select the clock generator
mode in SDCLK Frequency Select. If the Programmable Clock Mode is supported (nonzero value is set to Clock Multiplier in the Capabilities register), this bit attribute is RW,
and if not supported, this bit attribute is RO and zero is read. This bit depends on the
setting of Preset Value Enable in the Host Control 2 register. If the Preset Value Enable =
0, this bit is set by Host Driver. If the Preset Value Enable = 1, this bit is automatically
set to a value specified in one of Preset Value registers.
1 Programmable Clock Mode
0 Divided Clock Mode
4: 3
00b
RO
RSVD (rsvd): Reserved
2
0b
RW
SD Clock Enable (sd_clk_en): The Host Controller shall stop SDCLK when writing this
bit to 0. SDCLK Frequency Select can be changed when this bit is 0. Then, the Host
Controller shall maintain the same clock frequency until SDCLK is stopped (Stop at
SDCLK=0). If the Card Inserted in the Present State register is cleared, this bit shall be
cleared.
1 Enable
0 Disable
1
0b
RO
Internal Clock Stable (int_clk_stable): This bit is set to 1 when SD Clock is stable
after writing to Internal Clock Enable in this register to 1. The SD Host Driver shall wait
to set SD Clock Enable until this bit is set to 1. Note: This is useful when using PLL for a
clock oscillator that requires setup time.
1 Ready
0 Not Ready
0b
RW
Internal Clock Enable (int_clk_en): This bit is set to 0 when the Host Driver is not
using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host
Controller should stop its internal clock to go very low power state. Still, registers shall
be able to be read and written. Clock starts to oscillate when this bit is set to 1. When
clock oscillation is stable, the Host Controller shall set Internal Clock Stable in this
register to 1. This bit shall not affect card detection.
1 Oscillate
0 Stop
0
17.6.17
Timeout Control Register (TIMEOUT_CTL)—Offset 2Eh
At the initialization of the Host Controller, the Host Driver shall set the Data Timeout
Counter Value according to the Capabilities register.
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
TIMEOUT_CTL: [BAR0] + 2Eh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
0
0
reserved
0
4
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0
0
0
0
0
0
data_timeout_cnt_val
7
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Bit
Range
Default &
Access
7: 4
0h
RO
Reserved (reserved): Reserved
0h
RW
Data Timeout Counter Value (data_timeout_cnt_val): This value determines the
interval by which DAT line time-outs are detected. Refer to the Data Time-out Error in
the Error Interrupt Status register for information on factors that dictate time-out
generation. Time-out clock frequency will be generated by dividing the sdclockTMCLK by
this value. When setting this register, prevent inadvertent time-out events by clearing
the Data Time-out Error Status Enable (in the Error Interrupt Status Enable register).
1111 - Reserved
1110 - TMCLK * 2^27
--0001 - TMCLK * 2^14
0000 - TMCLK * 2^13
3: 0
17.6.18
Description
Software Reset Register (SW_RST)—Offset 2Fh
A reset pulse is generated when writing 1 to each bit of this register. After completing
the reset, the Host Controller shall clear each bit. Because it takes some time to
complete software reset, the SD Host Driver shall confirm that these bits are 0.
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
SW_RST: [BAR0] + 2Fh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
0
0
0
Bit
Range
Default &
Access
7: 3
0h
RO
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0
0
0
sw_rst_all
0
rsvd
0
0
sw_rst_cmd_ln
4
sw_rst_dat_ln
7
Description
RSVD (rsvd): Reserved
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
2
1
0
17.6.19
Default &
Access
Description
0b
RW
Software Reset For DAT Line (sw_rst_dat_ln): Only part of data circuit is reset.
The following registers and bits are cleared by this bit:
- Buffer Data Port Register: Buffer is cleared and Initialized.
- Present State register
Buffer read Enable
Buffer write Enable
Read Transfer Active
Write Transfer Active
DAT Line Active
Command Inhibit (DAT)
- Block Gap Control register
Continue Request
Stop At Block Gap Request
- Normal Interrupt Status register
Buffer Read Ready
Buffer Write Ready
Block Gap Event
Transfer Complete
1 - Reset
0 - Work
0h
RW
Software Reset For CMD Line (sw_rst_cmd_ln): Only part of command circuit is
reset. The following registers and bits are cleared by this bit:
- Present State register
Command Inhibit (CMD)
- Normal Interrupt Status register
Command Complete
1 Reset
0 Work
0b
RW
Software Reset For All (sw_rst_all): This reset affects the entire Host Controller
except for the card detection circuit. Register bits of type ROC, RW, RW1C, RWAC are
cleared to 0. During its initialization, the Host Driver shall set this bit to 1 to reset the
Host Controller. The Host Controller shall reset this bit to 0 when Capabilities registers
are valid and the Host Driver can read them. Additional use of Software Reset For All
may not affect the value of the Capabilities registers. If this bit is set to 1, the host
driver should issue reset command and reinitialize the SD card.
1 Reset
0 Work
Normal Interrupt Status Register (NML_INT_STATUS)—Offset
30h
The Normal Interrupt Status Enable affects reads of this register, but Normal Interrupt
Signal Enable does not affect these reads. An interrupt is generated when the Normal
Interrupt Signal Enable is enabled and at least one of the status bits is set to 1. Writing
1 to a bit of RW1C attribute clears it; writing 0 keeps the bit unchanged. Writing 1 to a
bit of ROC attribute keeps the bit unchanged. More than one status can be cleared with
a single register write. The Card Interrupt is cleared when the card stops asserting the
interrupt; that is, when the Card Driver services the interrupt condition.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
NML_INT_STATUS: [BAR0] + 30h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
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Datasheet
633
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
int_b
int_a
crd_int
crd_rm
0
0
0
0
0
0
0
cmd_comp
0
tx_comp
0
blk_gap_event
0
dma_int
0
0
buf_wr_rdy
0
buf_rd_rdy
0
crd_ins
0
int_c
4
re_tune
0
8
boot_ck_rcv
0
boot_ter_int
12
err_int
15
Default &
Access
Description
15
0b
RO
Error Interrupt (err_int): If any of the bits in the Error Interrupt Status Register are
set, then this bit is set. Therefore the HD can test for an error by checking this bit first.
0 - No Error. 1 - Error.
14
0h
RW/1C
Boot Terminate Interrupt (boot_ter_int): This status is set if the boot operation get
terminated. 0 - Boot operation is not terminated. 1 - Boot operation is terminated
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
13
0h
RW/1C
Boot Acknowledge Received (boot_ck_rcv): This status is set if the boot
acknowledge is received from device. 0 - Boot ack is not received. 1 - Boot ack is
received. NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
12
0h
RO
Re-Tuning Event (re_tune): This status is set if Re-Tuning Request in the Present
State register changes from 0 to 1. Host Controller requests Host Driver to perform retuning for next data transfer. Current data transfer (not large block count) can be
completed without re-tuning. 1 - Re-Tuning should be performed, 0 - Re-Tuning is not
required
11
0h
RO
INT_C (int_c): This status is set if INT_C is enabled and INT_C# pin is in low level.
Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_C interrupt
factor
10
0h
RO
INT_B (int_b): This status is set if INT_B is enabled and INT_B# pin is in low level.
Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_B interrupt
factor
9
0h
RO
INT_A (int_a): This status is set if INT_A is enabled and INT_A# pin is in low level.
Writing this bit to 1 does not clear this bit. It is cleared by resetting the INT_A interrupt
factor
8
0b
RO
Card Interrupt (crd_int): Writing this bit to 1 does not clear this bit. It is cleared by
resetting the SD card interrupt factor. In 1-bit mode, the HC shall detect the Card
Interrupt without SD Clock to support wakeup. In 4-bit mode, the card interrupt signal
is sampled during the interrupt cycle, so there are some sample delays between the
interrupt signal from the card and the interrupt to the Host system. when this status has
been set and the HD needs to start this interrupt service, Card Interrupt Status Enable
in the Normal Interrupt Status register shall be set to 0 in order to clear the card
interrupt statuses latched in the HC and stop driving the Host System. After completion
of the card interrupt service (the reset factor in the SD card and the interrupt signal
may not be asserted), set Card Interrupt Status Enable to 1 and start sampling the
interrupt signal again. Interrupt detected by DAT[1] is supported when there is a card
per slot. In case of shared bus, interrupt pins are used to detect interrupts. If 000b is
set to Interrupt Pin Select in the Shared Bus Control register, this status is effective.
Non-zero value is set to Interrupt Pin Select, INT_A, INT_B or INT_C is then used to
device interrupts. 0 - No Card Interrupt, 1 - Generate Card Interrupt
7
0b
RW/1C
Card Removal (crd_rm): This status is set if the Card Inserted in the Present State
register changes from 1 to 0. When the HD writes this bit to 1 to clear this status the
status of the Card Inserted in the Present State register should be confirmed. Because
the card detect may possibly be changed when the HD clear this bit an Interrupt event
may not be generated. 0 - Card State Stable or Debouncing, 1 - Card Removed
6
0b
RW/1C
Card Insertion (crd_ins): This status is set if the Card Inserted in the Present State
register changes from 0 to 1. When the HD writes this bit to 1 to clear this status the
status of the Card Inserted in the Present State register should be confirmed. Because
the card detect may possibly be changed when the HD clear this bit an Interrupt event
may not be generated. 0 - Card State Stable or Debouncing, 1 - Card Inserted
5
0b
RW/1C
Buffer Read Ready (buf_rd_rdy): This status is set if the Buffer Read Enable changes
from 0 to 1. Buffer Read Ready is set to 1 for every CMD19 execution in tuning
procedure. 0 - Not Ready to read Buffer. 1 - Ready to read Buffer.
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Datasheet
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Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Description
4
0b
RW/1C
Buffer Write Ready (buf_wr_rdy): This status is set if the Buffer Write Enable
changes from 0 to 1. 0 - Not Ready to Write Buffer. 1 - Ready to Write Buffer.
3
0b
RW/1C
DMA Interrupt (dma_int): This status is set if the HC detects the Host DMA Buffer
Boundary in the Block Size register. 0 - No DMA Interrupt, 1 - DMA Interrupt is
Generated
0b
RW/1C
Block Gap Event (blk_gap_event): If the Stop At Block Gap Request in the Block Gap
Control Register is set, this bit is set. Read Transaction: This bit is set at the falling edge
of the DAT Line Active Status (When the transaction is stopped at SD Bus timing. The
Read Wait must be supported in order to use this function). Write Transaction: This bit is
set at the falling edge of Write Transfer Active Status (After getting CRC status at SD
Bus timing). 0 - No Block Gap Event, 1 - Transaction stopped at Block Gap
0b
RW/1C
Transfer Complete (tx_comp): This bit is set when a read / write transfer and a
command with busy is completed.
(1) In the case of a Read Transaction
This bit is set at the falling edge of Read Transfer Active Status. This interrupt is
generated in two cases. The first is when a data transfer is completed as specified by
data length (After the last data has been read to the Host System). The second is when
data has stopped at the block gap and completed the data transfer by setting the Stop
At Block Gap Request in the Block Gap Control register (After valid data has been read
to the Host System). Refer to Section 3.12.3 of SD Host Controller Simplified
Specification Version 3.00 for more details on the sequence of events.
(2) In the case of a Write Transaction
This bit is set at the falling edge of the DAT Line Active Status. This interrupt is
generated in two cases. The first is when the last data is written to the SD card as
specified by data length and the busy signal released. The second is when data transfers
are stopped at the block gap by setting Stop At Block Gap Request in the Block Gap
Control register and data transfers completed. (After valid data is written to the SD card
and the busy signal released). Refer to Section 3.12.4 for more details on the sequence
of events.
(3) In the case of a command with busy
This bit is set when busy is de-asserted. Refer to DAT Line Active and Command Inhibit
(DAT) in the Present State register. Table on page 66 of SD Host Controller Simplified
Specification Version 3.00, Relation between Transfer Complete and Data Timeout Error,
shows that Transfer Complete has higher priority than Data Timeout Error. If both bits
are set to 1, execution of a command can be considered to be completed.
1 Command execution is completed
0 Not complete
While performing tuning procedure (Execute Tuning is set to 1), Transfer Complete is
not set to 1.
0b
RW/1C
Command Complete (cmd_comp): This bit is set when get the end bit of the
command response. Auto CMD12 and Auto CMD23 consist of two responses. Command
Complete is not generated by the response of CMD12 or CMD23 but generated by the
response of a read/write command. Refer to Command Inhibit (CMD) in the Present
State register for how to control this bit. Table on page 67 of SD Host Controller
Simplified Specification Version 3.00, Relation between command complete and
command time-out error, shows that Command Timeout Error has higher priority than
Command Complete. If both bits are set to 1, it can be considered that the response
was not received correctly.
1 Command complete 0 No command complete
2
1
0
17.6.20
Default &
Access
Error Interrupt Status Register (ERR_INT_STATUS)—Offset 32h
Signals defined in this register can be enabled by the Error Interrupt Status Enable
register, but not by the Error Interrupt Signal Enable register. The interrupt is
generated when the Error Interrupt Signal Enable is enabled and at least one of the
statuses is set to 1. Writing to 1 clears the bit and writing to 0 keeps the bit unchanged.
More than one status can be cleared at the one register write.
Access Method
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
635
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Type: Memory Mapped I/O Register
(Size: 16 bits)
ERR_INT_STATUS: [BAR0] + 32h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
adma_err
cmd12_err
cur_limit_err
0
0
0
0
0
0
0
cmd_timeout_err
0
cmd_crc_err
0
cmd_end_bit_err
0
cmd_index_err
0
0
data_timeout_err
0
data_crc_err
0
data_end_bit_err
0
tune_err
4
rsvd
0
vend_spec_err_status
0
8
tgt_rsp_err
12
ceata_err
15
Bit
Range
Default &
Access
15: 14
00b
RW
Vendor Specific Error Status (vend_spec_err_status): Reserved
13
0b
RW
CEATA Error Status (ceata_err): Occurs when ATA command termination has
occurred due to an error condition the device has encountered. 0 - no error, 1 - error
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
12
0b
RW
Target Response Error (tgt_rsp_err): Occurs when detecting ERROR in m_hresp
(dma transaction) 0 - no error, 1 - error NOTE: Not part of the SD Host Controller
Simplified Specification Version 3.00
11
0b
RO
RSVD (rsvd): Reserved
10
0b
RW
Tuning Error (tune_err): This bit is set when an unrecoverable error is detected in a
tuning circuit except during tuning procedure (Occurrence of an error during tuning
procedure is indicated by Sampling Select). By detecting Tuning Error, Host Driver needs
to abort a command executing and perform tuning. To reset tuning circuit, Sampling
Clock shall be set to 0 before executing tuning procedure. The Tuning Error is higher
priority than the other error interrupts generated during data transfer. By detecting
Turning Error, the Host Driver should discard data transferred by a current read/write
command and retry data transfer after the Host Controller retrieved from tuning circuit
error. 1 - Error, 0 - No Error
9
0b
RW
ADMA Error (adma_err): This bit is set when the Host Controller detects errors during
ADMA based data transfer. The state of the ADMA at an error occurrence is saved in the
ADMA Error Status Register. 1 - Error, 0 - No Error
8
0b
RW
Auto CMD Error (cmd12_err): Auto CMD12 and Auto CMD23 use this error status.
This bit is set when detecting that one of the bits D00-D04 in Auto CMD Error Status
register has changed from 0 to 1. In case of Auto CMD12, this bit is set to 1, not only
when the errors in Auto CMD12 occur but also when Auto CMD12 is not executed due to
the previous command error. 0 - No Error, 1 - Error
7
0b
RW
Current Limit Error (cur_limit_err): By setting the SD Bus Power bit in the Power
Control Register, the HC is requested to supply power for the SD Bus. If the HC supports
the Current Limit Function, it can be protected from an Illegal card by stopping power
supply to the card in which case this bit indicates a failure status. Reading 1 means the
HC is not supplying power to SD card due to some failure. Reading 0 means that the HC
is supplying power and no error has occurred. This bit shall always set to be 0, if the HC
does not support this function. 0 - No Error, 1 - Power Fail
6
0b
RW
Data End Bit Error (data_end_bit_err): Occurs when detecting 0 at the end bit
position of read data which uses the DAT line or the end bit position of the CRC status. 0
- No Error, 1 - Error
5
0b
RW
Data CRC Error (data_crc_err): Occurs when detecting CRC error when transferring
read data which uses the DAT line or when detecting the Write CRC Status having a
value of other than 010. 0 - No Error, 1 - Error
Intel® Quark™ SoC X1000
Datasheet
636
Description
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
17.6.21
Default &
Access
Description
4
0b
RW
Data Timeout Error (data_timeout_err): Occurs when detecting one of following
timeout conditions. 1. Busy Time-out for R1b, R5b type. 2. Busy Time-out after Write
CRC status 3. Write CRC status Time-out 4. Read Data Time-out 0 - No Error, 1 Timeout
3
0b
RW
Command Index Error (cmd_index_err): Occurs if a Command Index error occurs
in the Command Response. 0 - No Error, 1 - Error
2
0b
RW
Command End Bit Error (cmd_end_bit_err): Occurs when detecting that the end bit
of a command response is 0. 0 - No Error, 1 - End Bit Error Generated
1
0b
RW
Command CRC Error (cmd_crc_err): Command CRC Error is generated in two cases.
1. If a response is returned and the Command Time-out Error is set to 0, this bit is set
to 1 when detecting a CRT error in the command response 2. The HC detects a CMD line
conflict by monitoring the CMD line when a command is issued. If the HC drives the CMD
line to 1 level, but detects 0 level on the CMD line at the next SDCLK edge, then the HC
shall abort the command (Stop driving CMD line) and set this bit to 1. The Command
Time-out Error shall also be set to 1 to distinguish CMD line conflict. 0 - No Error, 1 CRC Error Generated
0
0b
RW
Command Timeout Error (cmd_timeout_err): Occurs only if the no response is
returned within 64 SDCLK cycles from the end bit of the command. If the HC detects a
CMD line conflict, in which case Command CRC Error shall also be set. This bit shall be
set without waiting for 64 SDCLK cycles because the command will be aborted by the
HC. 0 - No Error, 1 - Timeout
Normal Interrupt Status Enable (NRM_INT_STATUS_EN)—
Offset 34h
Setting to 1 enables Interrupt Status.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
NRM_INT_STATUS_EN: [BAR0] + 34h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
int_b_stat_en
int_a_stat_en
crd_int_stat_en
crd_rm_stat_en
Default &
Access
0
0
0
0
0
0
0
cmd_comp_stat_en
0
tx_comp_stat_en
0
blk_gap_event_stat_en
0
0
dma_int_stat_en
0
buf_wr_rdy_stat_en
0
buf_rd_rdy_stat_en
0
crd_ins_stat_en
0
int_c_stat_en
4
re_tune_stat_en
0
8
boot_ack_rcv_stat_en
0
boot_ter_int_stat_en
12
fixed_0
15
Description
15
0h
RO
Fixed to 0 (fixed_0): The HC shall control error Interrupts using the Error Interrupt
Status Enable register.
14
0h
RW
Boot Terminate Interrupt Status Enable (boot_ter_int_stat_en): 0 - Masked, 1 Enabled NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
13
0h
RW
Boot ACK Receive Enable (boot_ack_rcv_stat_en): 0 - Masked, 1 - Enabled NOTE:
Not part of the SD Host Controller Simplified Specification Version 3.00
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
637
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
17.6.22
Default &
Access
Description
12
0h
RW
Re-Tuning Event Status Enable (re_tune_stat_en): 0 - Masked, 1 - Enabled
11
0h
RW
INT_C Status Enable (int_c_stat_en): If this bit is set to 0, the Host Controller shall
clear the interrupt request to the System. The Host Driver may clear this bit before
servicing the INT_C and may set this bit again after all interrupt requests to INT_C pin
are cleared to prevent inadvertent interrupts.
10
0h
RW
INT_B Status Enable (int_b_stat_en): If this bit is set to 0, the Host Controller shall
clear the interrupt request to the System. The Host Driver may clear this bit before
servicing the INT_B and may set this bit again after all interrupt requests to INT_B pin
are cleared to prevent inadvertent interrupts.
9
0h
RW
INT_A Status Enable (int_a_stat_en): If this bit is set to 0, the Host Controller shall
clear the interrupt request to the System. The Host Driver may clear this bit before
servicing the INT_A and may set this bit again after all interrupt requests to INT_A pin
are cleared to prevent inadvertent interrupts.
8
0b
RW
Card Interrupt Status Enable (crd_int_stat_en): If this bit is set to 0, the HC shall
clear Interrupt request to the System. The Card Interrupt detection is stopped when this
bit is cleared and restarted when this bit is set to 1. The HD may clear the Card
Interrupt Status Enable before servicing the Card Interrupt and may set this bit again
after all Interrupt requests from the card are cleared to prevent inadvertent Interrupts.
0 - Masked, 1 - Enabled
7
0h
RW
Card Removal Status Enable (crd_rm_stat_en): 0 - Masked, 1 - Enabled
6
0h
RW
Card Insertion Status Enable (crd_ins_stat_en): 0 - Masked, 1 - Enabled
5
0h
RW
Buffer Read Ready Status Enable (buf_rd_rdy_stat_en): 0 - Masked, 1 - Enabled
4
0h
RW
Buffer Write Ready Status Enable (buf_wr_rdy_stat_en): 0 - Masked, 1 - Enabled
3
0h
RW
DMA Interrupt Status Enable (dma_int_stat_en): 0 - Masked, 1 - Enabled
2
0h
RW
Block Gap Event Status Enable (blk_gap_event_stat_en): 0 - Masked, 1 - Enabled
1
0h
RW
Transfer Complete Status Enable (tx_comp_stat_en): 0 - Masked, 1 - Enabled
0
0h
RW
Command Complete Status Enable (cmd_comp_stat_en): 0 - Masked, 1 - Enabled
Error Interrupt Status Enable Register (ERR_INT_STAT_EN)—
Offset 36h
Setting to 1 enables Interrupt Status.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
ERR_INT_STAT_EN: [BAR0] + 36h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Intel® Quark™ SoC X1000
Datasheet
638
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.6.23
adma_err_stat_en
cmd12_err_stat_en
cur_limit_err_stat_en
0
0
0
0
0
0
0
cmd_timeout_err_stat_en
0
cmd_crc_err_stat_en
0
cmd_end_bit_err_stat_en
0
0
cmd_ind_err_stat_en
0
data_timeout_err_stat_en
0
data_crc_err_stat_en
0
data_end_bit_err_stat_en
0
tune_err_stat_en
4
rsvd
0
rsvd0
0
8
tgt_rsp_err_en
12
ceata_err_en
15
Bit
Range
Default &
Access
15: 14
0b
RO
Vendor Specific Error Status Enable (rsvd0): Reserved
13
0b
RW
CEATA Error Status Enable (ceata_err_en): 0 - Masked, 1 - Enabled NOTE: Not part
of the SD Host Controller Simplified Specification Version 3.00
12
0b
RW
Target Response Error Status Enable (tgt_rsp_err_en): 0 - Masked, 1 - Enabled
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
11
0h
RO
RSVD (rsvd): Reserved
10
0h
RW
Tuning Error Status Enable (tune_err_stat_en): 0 - Masked, 1 - Enabled
9
0h
RW
ADMA Error Status Enable (adma_err_stat_en): 0 - Masked, 1 - Enabled
8
0h
RW
Auto CMD12 Error Status Enable (cmd12_err_stat_en): 0 - Masked, 1 - Enabled
7
0h
RW
Current Limit Error Status Enable (cur_limit_err_stat_en): 0 - Masked, 1 Enabled
6
0h
RW
Data End Bit Error Status Enable (data_end_bit_err_stat_en): 0 - Masked, 1 Enabled
5
0h
RW
Data CRC Error Status Enable (data_crc_err_stat_en): 0 - Masked, 1 - Enabled
4
0h
RW
Data Timeout Error Status Enable (data_timeout_err_stat_en): 0 - Masked, 1 Enabled
3
0h
RW
Command Index Error Status Enable (cmd_ind_err_stat_en): 0 - Masked, 1 Enabled
2
0h
RW
Command End Bit Error Status Enable (cmd_end_bit_err_stat_en): 0 - Masked,
1 - Enabled
1
0h
RW
Command CRC Error Status Enable (cmd_crc_err_stat_en): 0 - Masked, 1 Enabled
0
0h
RW
Command Timeout Error Status Enable (cmd_timeout_err_stat_en): 0 Masked, 1 - Enabled
Description
Normal Interrupt Signal Enable Register (NRM_INT_SIG_EN)—
Offset 38h
This register is used to select which interrupt status is indicated to the Host System as
the interrupt. These status bits all share the same1 bit interrupt line. Setting any of
these bits to 1 enables interrupt generation.
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
639
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
NRM_INT_SIG_EN: [BAR0] + 38h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
int_b_sig_en
int_a_sig_en
crd_int_sig_en
crd_rm_sig_en
Default &
Access
0
0
0
0
0
0
0
cmd_comp_sig_en
0
tx_comp_sig_en
0
blk_gap_event_sig_en
0
dma_int_sig_en
0
0
buf_wr_rdy_sig_en
0
buf_rd_rdy_sig_en
0
crd_ins_sig_en
0
int_c_sig_en
4
re_tune_sig_en
0
8
boot_ack_rcv_sig_en
0
boot_ter_int_sig_en
12
fixed_0
15
Description
15
0h
RO
Fixed to 0 (fixed_0): The HD shall control error Interrupts using the Error Interrupt
Signal Enable register.
14
0h
RW
Boot Terminate Interrupt Signal Enable (boot_ter_int_sig_en): 0 - Masked, 1 Enabled NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
13
0h
RW
Boot ACK Received Signal Enable (boot_ack_rcv_sig_en): 0 - Masked, 1 Enabled NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
12
0h
RW
Re-Tuning Event Signal Enable (re_tune_sig_en): 0 - Masked, 1 - Enabled
11
0h
RW
INT_C Signal Enable (int_c_sig_en): 0 - Masked, 1 - Enabled
10
0h
RW
INT_B Signal Enable (int_b_sig_en): 0 - Masked, 1 - Enabled
9
0h
RW
INT_A Signal Enable (int_a_sig_en): Reserved.
8
0h
RW
Card Interrupt Signal Enable (crd_int_sig_en): 0 - Masked, 1 - Enabled
7
0h
RW
Card Removal Signal Enable (crd_rm_sig_en): 0 - Masked, 1 - Enabled
6
0h
RW
Card Insertion Signal Enable (crd_ins_sig_en): 0 - Masked, 1 - Enabled
5
0h
RW
Buffer Read Ready Signal Enable (buf_rd_rdy_sig_en): 0 - Masked, 1 - Enabled
4
0h
RW
Buffer Write Ready Signal Enable (buf_wr_rdy_sig_en): 0 - Masked, 1 - Enabled
3
0h
RW
DMA Interrupt Signal Enable (dma_int_sig_en): 0 - Masked, 1 - Enabled
2
0h
RW
Block Gap Event Signal Enable (blk_gap_event_sig_en): 0 - Masked, 1 - Enabled
1
0h
RW
Transfer Complete Signal Enable (tx_comp_sig_en): 0 - Masked, 1 - Enabled
Intel® Quark™ SoC X1000
Datasheet
640
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
0
17.6.24
Default &
Access
Description
0h
RW
Command Complete Signal Enable (cmd_comp_sig_en): 0 - Masked, 1 - Enabled
Error Interrupt Signal Enable Register (ERR_INT_SIG_EN)—
Offset 3Ah
This register is used to select which interrupt status is notified to the Host System as
the interrupt. These status bits all share the same 1 bit interrupt line. Setting any of
these bits to 1 enables interrupt generation.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
ERR_INT_SIG_EN: [BAR0] + 3Ah
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
adma_err_sig_en
cmd12_err_sig_en
cur_limit_err_sig_en
0
0
0
0
0
0
0
cmd_timeout_err_stat_en
0
cmd_crc_err_stat_en
0
cmd_end_bit_err_stat_en
0
0
cmd_ind_err_stat_en
0
data_timeout_err_stat_en
0
data_crc_err_sig_en
0
data_end_bit_err_sig_en
0
tune_err_sig
4
rsvd
0
rsvd0
0
8
tgt_err_rsp_sig_en
12
ceata_err_sig_en
15
Bit
Range
Default &
Access
15: 14
0b
RO
Vendor Specific Error Signal Enable (rsvd0): Reserved
13
0b
RW
CEATA Error Signal Enable (ceata_err_sig_en): 0 - Masked, 1 - Enabled NOTE: Not
part of the SD Host Controller Simplified Specification Version 3.00
12
0b
RW
Target Response Error Signal Enable (tgt_err_rsp_sig_en): 0 - Masked, 1 Enabled NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
11
0h
RO
RSVD (rsvd): Reserved
10
0h
RW
Tuning Error Signal Enable (tune_err_sig): 0 - Masked, 1 - Enabled
9
0h
RW
ADMA Error Signal Enable (adma_err_sig_en): 0 - Masked, 1 - Enabled
8
0h
RW
Auto CMD12 Error Signal Enable (cmd12_err_sig_en): 0 - Masked, 1 - Enabled
7
0h
RW
Current Limit Error Signal Enable (cur_limit_err_sig_en): 0 - Masked, 1 - Enabled
6
0h
RW
Data End Bit Error Signal Enable (data_end_bit_err_sig_en): 0 - Masked, 1 Enabled
August 2015
Document Number: 329676-005US
Description
Intel® Quark™ SoC X1000
Datasheet
641
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
17.6.25
Default &
Access
Description
5
0h
RW
Data CRC Error Signal Enable (data_crc_err_sig_en): 0 - Masked, 1 - Enabled
4
0h
RW
Data Timeout Error Signal Enable (data_timeout_err_stat_en): 0 - Masked, 1 Enabled
3
0h
RW
Command Index Error Signal Enable (cmd_ind_err_stat_en): 0 - Masked, 1 Enabled
2
0h
RW
Command End Bit Error Signal Enable (cmd_end_bit_err_stat_en): 0 - Masked,
1 - Enabled
1
0h
RW
Command CRC Error Signal Enable (cmd_crc_err_stat_en): 0 - Masked, 1 Enabled
0
0h
RW
Command Timeout Error Signal Enable (cmd_timeout_err_stat_en): 0 - Masked,
1 - Enabled
Auto CMD12 Error Status Register (CMD12_ERR_STAT)—Offset
3Ch
This register is used to indicate CMD12 response error of Auto CMD12 and CMD23
response error of Auto CMD23. The Host driver can determine what kind of Auto
CMD12 / CMD23 errors occur by this register. Auto CMD23 errors are indicated in bit
04-01.This register is valid only when the Auto CMD Error is set.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
CMD12_ERR_STAT: [BAR0] + 3Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
Default &
Access
0
0
0
0
0
0
0
0
0
cmd12_not_exe
0
cmd12_timeout_err
0
cmd12_crc_err
0
cmd12_end_bit_err
0
0
cmd12_ind_err
0
4
rsvd2
0
8
rsvd1
0
12
cmd_not_iss_cmd12_err
15
Description
15: 8
0h
RO
RSVD1 (rsvd1): Reserved
7
0b
RO
Command Not Issued By Auto CMD12 Error (cmd_not_iss_cmd12_err):
CMD_wo_DAT is not executed due to an Auto CMD12 error (D04 - D01) in this register.
This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 0 - No Error, 1 Not Issued
6: 5
0h
RO
RSVD2 (rsvd2): Reserved
Intel® Quark™ SoC X1000
Datasheet
642
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
4
0b
RO
Auto CMD Index Error (cmd12_ind_err): Occurs if the Command Index error occurs
in response to a command. 0 - No Error, 1 - Error
3
0b
RO
Auto CMD End Bit Error (cmd12_end_bit_err): Occurs when detecting that the end
bit of command response is 0. 0 - No Error, 1 - End Bit Error Generated
2
0b
RO
Auto CMD CRC Error (cmd12_crc_err): Occurs when detecting a CRC error in the
command response. 0 - No Error, 1 - CRC Error Generated
1
0b
RO
Auto CMD Timeout Error (cmd12_timeout_err): Occurs if the no response is
returned within 64 SDCLK cycles from the end bit of the command. If this bit is set to 1,
the other error status bits (D04 - D02) are meaningless. 0 - No Error, 1 - Timeout
0b
RO
Auto CMD12 Not Executed (cmd12_not_exe): If memory multiple block data
transfer is not started due to command error, this bit is not set because it is not
necessary to issue Auto CMD12. Setting this bit to 1 means the HC cannot issue Auto
CMD12 to stop memory multiple block transfer due to some error. If this bit is set to 1,
other error status bits (D04 - D01) are meaningless. This bit is set to 0 when Auto CMD
Error is generated by Auto CMD23. 0 - Executed, 1 - Not Executed
0
17.6.26
Host Control 2 Register (HOST_CTRL_2)—Offset 3Eh
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
HOST_CTRL_2: [BAR0] + 3Eh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
0
4
0
0
0
0
0
0
0
0
0
uhs_mode
0
driver_strength
0
vl
8
0
execute_tuning
0
sampling_clock
0
rsvd0
0
async_int
12
0
preset_value
15
Default &
Access
Description
0b
RW
Preset Value Enable (preset_value): Host Controller Version 3.00 supports this bit.
As the operating SDCLK frequency and I/O driver strength depend on the Host System
implementation, it is difficult to determine these parameters in the Standard Host
Driver. When Preset Value Enable is set to automatic This bit enables the functions
defined in the Preset Value registers. 1 Automatic Selection by Preset Value are Enabled
0 SDCLK and Driver Strength are controlled by Host Driver If this bit is set to 0, SDCLK
Frequency Select, Clock Generator Select in the Clock Control register and Driver
Strength Select in Host Control 2 register are set by Host Driver. If this bit is set to 1,
SDCLK Frequency Select, Clock Generator Select in the Clock Control register and Driver
Strength Select in Host Control 2 register are set by Host Controller as specified in the
Preset Value registers.
14
0b
RW
Asynchronous Interrupt Enable (async_int): This bit can be set to 1 if a card
support asynchronous interrupt and Asynchronous Interrupt Support is set to 1 in the
Capabilities register. Asynchronous interrupt is effective when DAT[1] interrupt is used
in 4-bit SD mode (and zero is set to Interrupt Pin Select in the Shared Bus Control
register). If this bit is set to 1, the Host Driver can stop the SDCLK during asynchronous
interrupt period to save power. During this period, the Host Controller continues to
deliver Card Interrupt to the host when it is asserted by the Card. 1 Enabled, 0 Disabled
13: 8
00h
RO
RSVD0 (rsvd0): Reserved
15
August 2015
Document Number: 329676-005US
Intel® Quark™ SoC X1000
Datasheet
643
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
Default &
Access
Description
7
0b
RW
Sampling Clock Select (sampling_clock): This bit is set by tuning procedure when
Execute Tuning is cleared. Writing 1 to this bit is meaningless and ignored. Setting 1
means that tuning is completed successfully and setting 0 means that tuning is failed.
Host Controller uses this bit to select sampling clock to receive CMD and DAT. This bit is
cleared by writing 0. Change of this bit is not allowed while the Host Controller is
receiving response or a read data block. 1 Tuned clock is used to sample data, 0 Fixed
clock is used to sample data
6
0b
RW/AC
Execute Tuning (execute_tuning): This bit is set to 1 to start tuning procedure and
automatically cleared when tuning procedure is completed. The result of tuning is
indicated to Sampling Clock Select. Tuning procedure is aborted by writing 0 for more
detail about tuning procedure. 1 Execute Tuning, 0 Not Tuned or Tuning Completed
5: 4
0b
RW
Driver Strength Select (driver_strength): Host Controller output driver in 1.8V
signaling is selected by this bit. In 3.3V signaling, this field is not effective. This field can
be set depends on Driver Type A, C and D support bits in the Capabilities register. This
bit depends on setting of Preset Value Enable. If Preset Value Enable = 0, this field is set
by Host Driver. If Preset Value Enable = 1, this field is automatically set by a value
specified in the one of Preset Value registers. 00b Driver Type B is Selected (Default),
01b Driver Type A is Selected, 10b Driver Type C is Selected, 11b Driver Type D is
Selected
3
0b
RO
Reserved (vl): Reserved
0b
RW
UHS Mode Select (uhs_mode): This field is used to select one of UHS-I modes and
effective when 1.8V Signaling Enable is set to 1. If Preset Value Enable in the Host
Control 2 register is set to 1, Host Controller sets SDCLK Frequency Select, Clock
Generator Select in the Clock Control register and Driver Strength Select according to
Preset Value registers. In this case, one of preset value registers is selected by this field.
Host Driver needs to reset SD Clock Enable before changing this field to avoid
generating clock glitch. After setting this field, Host Driver sets SD Clock Enable again.
000b - SDR12, 001b - SDR25, 010b - SDR50, 011b - SDR104, 100b - DDR50, 101b 111 Reserved. When SDR50, SDR104 or DDR50 is selected for SDIO card, interrupt
detection at the block gap shall not be used. Read Wait timing is changed for these
modes. Refer to the SDIO Specification Version 3.00 for more detail.
2: 0
17.6.27
Capabilities Register (CAPABILITIES)—Offset 40h
This register provides the Host Driver with information specific to the Host Controller
implementation. The Host Controller may implement these values as fixed or loaded
from flash memory during power on initialization. Refer to Software Reset For All in the
Software Reset register for loading from flash memory and completion timing control.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
CAPABILITIES: [BAR0] + 40h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 01EC32B2h
Intel® Quark™ SoC X1000
Datasheet
644
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
0
0
0
0
1
1
0
0
1
0
1
0
1
1
0
0
0
1
0
timeout_clock_frequency
1
4
rsvd6
1
8
timeout_clock_unit
0
12
base_clock_frequency_sd_clk
1
max_block_length
volt_support_3p3v
suspend_resume_support
1
extended_media_bus_support
1
rsvd5
1
16
adma2_support
0
sdma_support
0
high_speed_support
0
volt_support_3p0v
0
20
rsvd4
0
24
volt_support_1p8v
0
slot_type
0
async_int_support
28
sys_bus_support_64b
31
Default &
Access
Description
0b
RO
Slot Type (slot_type): This field indicates usage of a slot by a specific Host System. (A
host controller register set is defined per slot.) Embedded slot for one device (01b)
means that only one non-removable device is connected to a SD bus slot. Shared Bus
Slot (10b) can be set if Host Controller supports Shared Bus Control register. The
Standard Host Driver controls only a removable card or one embedded device is
connected to a SD bus slot. If a slot is configured for shared bus (10b), the Standard
Host Driver does not control embedded devices connected to a shared bus. Shared bus
slot is controlled by a specific host driver developed by a Host System. 00b - Removable
Card Slot, 01b - Embedded Slot for One Device, 10b - Shared Bus Slot, 11b - Reserved
29
0b
RO
Asynchronous Interrupt Support (async_int_support): Refer to SDIO
Specification Version 3.00 about asynchronous interrupt. 1 - Asynchronous Interrupt
Supported, 0 - Asynchronous Interrupt Not Supported
28
0b
RO
64-bit System Bus Support (sys_bus_support_64b): 1 - supports 64 bit system
address, 0 - Does not support 64 bit system address
27
0b
RO
RSVD4 (rsvd4): Reserved
26
0b
RO
Voltage Support 1.8V (volt_support_1p8v): 0 - 1.8V Not Supported, 1 - 1.8V
Supported
25
0b
RO
Voltage Support 3.0V (volt_support_3p0v): 0 - 3.0V Not Supported, 1 - 3.0V
Supported
24
1b
RO
Voltage Support 3.3V (volt_support_3p3v): 0 - 3.3V Not Supported, 1 - 3.3V
Supported
23
1b
RO
Suspend/Resume Support (suspend_resume_support): This bit indicates whether
the HC supports Suspend / Resume functionality. If this bit is 0, the Suspend and
Resume mechanism are not supported and the HD shall not issue either Suspend /
Resume commands. 0 - Not Supported, 1 - Supported
22
1b
RO
SDMA Support (sdma_support): This bit indicates whether the HC is capable of using
DMA to transfer data between system memory and the HC directly. 0 - SDMA Not
Supported, 1 - SDMA Supported.
21
1b
RO
High Speed Support (high_speed_support): This bit indicates whether the HC and
the Host System support High Speed mode and they can supply SD Clock frequency
from 25MHz to 50 MHz (for SD)/ 20MHz to 52MHz (for MMC). 0 - High Speed Not
Supported, 1 - High Speed Supported
20
0b
RO
RSVD5 (rsvd5): Reserved
19
1b
RO
ADMA2 Support (adma2_support): 1 - ADMA2 support. 0 - ADMA2 not support
18
1b
RO
Extended Media Bus Support (extended_media_bus_support): This bit indicates
whether the Host Controller is capable of using 8-bit bus width mode. This bit is not
effective when Slot Type is set to 10b. In this case, refer to Bus Width Preset in the
Shared Bus resister. 1 - Extended Media Bus Supported, 0 - Extended Media Bus not
Supported
31: 30
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Document Number: 329676-005US
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Datasheet
645
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
17.6.28
Bit
Range
Default &
Access
Description
17: 16
00b
RO
Max Block Length (max_block_length): This value indicates the maximum block
size that the HD can read and write to the buffer in the HC. The buffer shall transfer this
block size without wait cycles. Three sizes can be defined as indicated below. 00 - 512
byte, 01 - 1024 byte, 10 - 2048 byte, 11 - 4096 byte
15: 8
32h
RO
Base Clock Frequency for SD Clock (base_clock_frequency_sd_clk): (1) 6-bit
Base Clock Frequency This mode is supported by the Host Controller Version 1.00 and
2.00. Upper 2-bit is not effective and always 0. Unit values are 1MHz. The supported
clock range is 10MHz to 63MHz. 11xx xxxxb - Not supported, 0011 1111b - 63MHz,
0000 0010b - 2MHz, 0000 0001b - 1MHz, 0000 0000b - Get information via another
method. (2) 8-bit Base Clock Frequency This mode is supported by the Host Controller
Version 3.00.Unit values are 1MHz. The supported clock range is 10MHz to 255MHz. FFh
- 255MHz, 02h - 2MHz, 01h - 1MHz, 00h - Get information via another method. If the
real frequency is 16.5MHz, the lager value shall be set 0001 0001b (17MHz) because
the Host Driver use this value to calculate the clock divider value (Refer to the SDCLK
Frequency Select in the Clock Control register.) and it shall not exceed upper limit of the
SD Clock frequency. If these bits are all 0, the Host System has to get information via
another method.
7
1b
RO
Timeout Clock Unit (timeout_clock_unit): This bit shows the unit of base clock
frequency used to detect Data Timeout Error. 0 - KHz, 1 - MHz
6
0b
RO
RSVD6 (rsvd6): Reserved
5: 0
32h
RO
Timeout Clock Frequency (timeout_clock_frequency): This bit shows the base
clock frequency used to detect Data Timeout Error. Not 0 - 1KHz to 63KHz or 1MHz to
63MHz, 000000b - Get Information via another method.
Capabilities Register 2 (CAPABILITIES_2)—Offset 44h
This register provides the host driver with information specific to the host controller
implementation.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
CAPABILITIES_2: [BAR0] + 44h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 03000000h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
sdr50_support
0
ddr104_support
0
rsvd3
0
0
ddr50_support
0
driver_type_c_sup
0
driver_type_a_sup
0
rsvd2
0
4
driver_type_d_sup
1
8
tim_cnt_for_retune
1
rsvd1
0
12
use_tuning_for_sdr50
0
16
retune_modes
0
20
clk_mult
0
spi_mode
0
24
rsvd0
0
28
spi_blk_mode
31
Bit
Range
Default &
Access
31: 26
0b
RO
RSVD0 (rsvd0): Reserved
1b
RO
SPI Block Mode (spi_blk_mode): SPI block mode. 0 - Not Supported, 1 - Supported
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
25
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Description
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
1b
RO
SPI Mode (spi_mode): SPI mode. 0 - Not Supported, 1 - Supported NOTE: Not part of
the SD Host Controller Simplified Specification Version 3.00
0b
RO
Clock Multiplier (clk_mult): This field indicates clock multiplier value of
programmable clock generator. Refer to Clock Control register. Setting 00h means that
Host Controller does not support programmable clock generator. FFh Clock Multiplier M
= 256, ...., 02h Clock Multiplier M = 3, 01h Clock Multiplier M = 2, 00h Clock Multiplier is
Not Supported
0b
RO
Re-Tuning Modes (retune_modes): This field defines the re-tuning capability of a
Host Controller and how to manage the data transfer length and a Re-Tuning Timer by
the Host Driver 00 - Mode1, 01 - Mode2, 10 - Mode3, 11 - Reserved. There are two retuning timings: Re-Tuning Request and expiration of a Re-Tuning Timer. By receiving
either timing, the Host Driver executes the re-tuning procedure just before a next
command issue
13
0b
RO
Use Tuning for SDR50 (use_tuning_for_sdr50): If this bit is set to 1, this Host
Controller requires tuning to operate SDR50. (Tuning is always required to operate
SDR104.) 1 SDR50 requires tuning 0, SDR50 does not require tuning
12
0b
RO
RSVD1 (rsvd1): Reserved
11: 8
0h
RO
Timer count for Re-Tuning (tim_cnt_for_retune): This field indicates an initial
value of the Re-Tuning Timer for Re-Tuning Mode 1 to 3. 0h - Get information via other
source, 1h = 1 seconds, 2h = 2 seconds, 3h = 4 seconds, 4h = 8 seconds, --, n = 2(n1) seconds, --, Bh = 1024 seconds, Fh - Ch = Reserved
7
0b
RO
RSVD2 (rsvd2): Reserved
6
0b
RO
Driver Type D Support (driver_type_d_sup): This bit indicates support of Driver
Type D for 1.8 Signaling. 1 - Driver Type D is Supported, 0 - Driver Type D is Not
Supported.
5
0b
RO
Driver Type C Support (driver_type_c_sup): This bit indicates support of Driver
Type C for 1.8 Signaling. 1 - Driver Type C is Supported, 0 - Driver Type C is Not
Supported.
4
0b
RO
Driver Type A Support (driver_type_a_sup): This bit indicates support of Driver
Type A for 1.8 Signaling. 1 - Driver Type A is Supported, 0 - Driver Type A is Not
Supported.
3
0b
RO
RSVD3 (rsvd3): Reserved
2
0b
RO
DDR50 Support (ddr50_support): 1 - DDR50 is Supported, 0 - DDR50 is Not
Supported
1
0b
RO
DDR104 Support (ddr104_support): 1 - DDR104 is Supported, 0 - DDR104 is Not
Supported
0
0b
RO
SDR50 Support (sdr50_support): If SDR104 is supported, this bit shall be set to 1.
Bit 40 indicates whether SDR50 requires tuning or not. 1 - SDR50 is Supported, 0 SDR50 is Not Supported
24
23: 16
15: 14
17.6.29
Maximum Current Capabilities Register (MAX_CUR_CAP)—
Offset 48h
These registers indicate maximum current capability for each voltage. The value is
meaningful if Voltage Support is set in the Capabilities register. If this information is
supplied by the Host System via another method, all Maximum Current Capabilities
register shall be 0.
Access Method
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Document Number: 329676-005US
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Datasheet
647
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Type: Memory Mapped I/O Register
(Size: 32 bits)
MAX_CUR_CAP: [BAR0] + 48h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000001h
0
0
0
0
0
0
0
0
0
0
17.6.30
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
1
max_cur_3p3v
0
20
rsvd
0
24
max_cur_3p0v
28
max_cur_1p8v
31
Bit
Range
Default &
Access
31: 24
0h
RO
RSVD (rsvd): Reserved
23: 16
00h
RO
Maximum Current for 1.8V (max_cur_1p8v): Maximum current capability for 1.8V
15: 8
00h
RO
Maximum Current for 3.0V (max_cur_3p0v): Maximum current capability for 3.0V
7: 0
01h
RO
Maximum Current for 3.3V (max_cur_3p3v): Maximum current capability for 3.3V
Description
Force Event Register for Auto CMD12 Error Status
(FORCE_EVENT_CMD12_ERR_STAT)—Offset 50h
The Force Event Register is not a physically implemented register. Rather, it is an
address at which the Auto CMD Error Status Register can be written. Writing 1 : set
each bit of the Auto CMD Error Status Register Writing 0 : no effect
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
FORCE_EVENT_CMD12_ERR_STAT: [BAR0] + 50h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Bit
Range
15: 8
Intel® Quark™ SoC X1000
Datasheet
648
0
4
0
Default &
Access
00h
RO
0
0
0
0
0
0
0
0
cmd_not_exe
0
cmd_timeout_err
0
cmd_crc_err
0
cmd_end_bit_err
8
0
cmd_ind_err
0
reserved
12
0
reserved0
0
non_cmd12_err
15
Description
Reserved0 (reserved0): Reserved
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
17.6.31
Default &
Access
Description
7
0b
RW
Force Event for Command Not Issued By Auto CMD12 Error (non_cmd12_err):
1 - Interrupt is generated, 0 - No interrupt
6: 5
00b
RO
Reserved (reserved): Reserved
4
0b
RW
Force Event for Auto CMD Index Error (cmd_ind_err): 1 - Interrupt is generated, 0
- No interrupt
3
0b
RW
Force Event for Auto CMD End Bit Error (cmd_end_bit_err): 1 - Interrupt is
generated, 0 - No interrupt
2
0b
RW
Force Event for Auto CMD CRC Error (cmd_crc_err): 1 - Interrupt is generated, 0 No interrupt
1
0b
RW
Force Event for Auto CMD Timeout Error (cmd_timeout_err): 1 - Interrupt is
generated, 0 - No interrupt
0
0b
RW
Force Event for Auto CMD Not Executed (cmd_not_exe): 1 - Interrupt is
generated, 0 - No interrupt
Force Event Register for Error Interrupt Status
(FORCE_EVENT_ERR_INT_STAT)—Offset 52h
The Force Event Register is not a physically implemented register. Rather, it is an
address at which the Error Interrupt Status register can be written. The effect of a write
to this address will be reflected in the Error Interrupt Status Register if the
corresponding bit of the Error Interrupt Status Enable Register is set. Writing 1 : set
each bit of the Error Interrupt Status Register Writing 0 : no effect Note: By setting this
register, the Error Interrupt can be set in the Error Interrupt Status register. In order to
generate interrupt signal, both the Error Interrupt Status Enable and Error Interrupt
Signal Enable shall be set.
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
FORCE_EVENT_ERR_INT_STAT: [BAR0] + 52h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
0
0
0
0
cmd_timeout_err
0
cmd_crc_err
0
cmd_end_bit_err
0
0
cmd_ind_err
0
data_timeout_err
0
data_crc_err
0
data_end_bit_err
0
cur_limit_err
0
cmd12_err
0
4
adma_err
0
8
rsvd
0
rsvd0
0
tgt_rsp_err
12
ceata_err
15
Bit
Range
Default &
Access
15: 14
00b
RO
Force Event for Vendor Specific Error Status (rsvd0): Reserved
0b
RW
Force Event for CEATA error (ceata_err): 1 - Interrupt is generated, 0 - No interrupt
13
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Document Number: 329676-005US
Description
Intel® Quark™ SoC X1000
Datasheet
649
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
Default &
Access
Description
0b
RW
Force Event for Target Response Error (tgt_rsp_err): 1 - Interrupt is generated, 0
- No interrupt
11: 10
0h
RO
RSVD (rsvd): Reserved
9
0h
RW
Force Event for ADMA Error (adma_err): 1 - Interrupt is generated, 0 - No interrupt
8
0h
RW
Force Event for Auto CMD Error (cmd12_err): 1 - Interrupt is generated, 0 - No
interrupt
7
0h
RW
Force Event for Current Limit Error (cur_limit_err): 1 - Interrupt is generated, 0 No interrupt
6
0h
RW
Force Event for Data End Bit Error (data_end_bit_err): 1 - Interrupt is generated,
0 - No interrupt
5
0h
RW
Force Event for Data CRC Error (data_crc_err): 1 - Interrupt is generated, 0 - No
interrupt
4
0h
RW
Force Event for Data Timeout Error (data_timeout_err): 1 - Interrupt is
generated, 0 - No interrupt
3
0h
RW
Force Event for Command Index Error (cmd_ind_err): 1 - Interrupt is generated,
0 - No interrupt
2
0h
RW
Force Event for Command End Bit Error (cmd_end_bit_err): 1 - Interrupt is
generated, 0 - No interrupt
1
0h
RW
Force Event for Command CRC Error (cmd_crc_err): 1 - Interrupt is generated, 0 No interrupt
0
0h
RW
Force Event for Command Timeout Error (cmd_timeout_err): 1 - Interrupt is
generated, 0 - No interrupt
12
17.6.32
ADMA Error Status Register (ADMA_ERR_STAT)—Offset 54h
When ADMA Error Interrupt is occurred, the ADMA Error States field in this register
holds the ADMA state and the ADMA System Address Register holds the address around
the error descriptor. For recovering the error, the Host Driver requires the ADMA state
to identify the error descriptor address as follows: ST_STOP: Previous location set in
the ADMA System Address register is the error descriptor address ST_FDS: Current
location set in the ADMA System Address register is the error descriptor address
ST_CADR: This sate is never set because do not generate ADMA error in this state.
ST_TFR: Previous location set in the ADMA System Address register is the error
descriptor address In case of write operation, the Host Driver should use ACMD22 to
get the number of written block rather than using this information, since unwritten data
may exist in the Host Controller. The Host Controller generates the ADMA Error
Interrupt when it detects invalid descriptor data (Valid=0) at the ST_FDS state. In this
case, ADMA Error State indicates that an error occurs at ST_FDS state. The Host Driver
may find that the Valid bit is not set in the error descriptor.
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
ADMA_ERR_STAT: [BAR0] + 54h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
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Datasheet
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August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
7
4
0
0
0
0
0
adma_err_state
Bit
Range
Default &
Access
7: 3
0h
RO
RSVD (rsvd): Reserved
2
0b
RO
ADMA Length Mismatch Error (adma_len_mis_err): This error occurs in the
following 2 cases. 1. While Block Count Enable being set, the total data length specified
by the Descriptor table is different from that specified by the Block Count and Block
Length. 2. Total data length can not be divided by the block length. 1 - Error, 0 - No
error
00b
RO
ADMA Error State (adma_err_state): This field indicates the state of ADMA when
error is occurred during ADMA data transfer. This field never indicates 10 because ADMA
never stops in this state. D01 D00: ADMA Error State when error is occurred Contents of
SYS_SDR register, 00 - ST_STOP (Stop DMA) Points next of the error descriptor, 01 ST_FDS (Fetch Descriptor) Points the error descriptor, 10 - Never set this state (Not
used), 11 - ST_TFR (Transfer Data) Points the next of the error descriptor
1: 0
17.6.33
0
adma_len_mis_err
0
rsvd
0
0
Description
ADMA System Address Register (ADMA_SYS_ADDR)—Offset
58h
This register contains the physical Descriptor address used for ADMA data transfer.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
ADMA_SYS_ADDR: [BAR0] + 58h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
adma_sys_addr
0
28
Bit
Range
31: 0
Default &
Access
Description
0h
RW
ADMA System Address (adma_sys_addr): This register holds byte address of
executing command of the Descriptor table. 32-bit Address Descriptor uses lower 32- bit
of this register. At the start of ADMA, the Host Driver shall set start address of the
Descriptor table. The ADMA increments this register address, which points to next line,
when every fetching a Descriptor line. When the ADMA Error Interrupt is generated, this
register shall hold valid Descriptor address depending on the ADMA state. The Host
Driver shall program Descriptor Table on 32-bit boundary and set 32-bit boundary
address to this register. ADMA2 ignores lower 2-bit of this register and assumes it to be
00b.
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Document Number: 329676-005US
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Datasheet
651
Intel® Quark™ SoC X1000—SDIO/SD/eMMC
17.6.34
initialization Preset Values Register (3.3v or 1.8v)
(PRESET_VALUE_0)—Offset 60h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_0: [BAR0] + 60h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0040h
12
0
0
rsvd
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
0b
RO
10
040h
RO
9: 0
17.6.35
0
0
0
0
4
0
1
0
0
0
0
0
0
0
sdclk_freq_sel_val
0
driver_strength_sel_val
0
8
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
Default Speed Preset Values Register (PRESET_VALUE_1)—
Offset 62h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_1: [BAR0] + 62h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0001h
Intel® Quark™ SoC X1000
Datasheet
652
0
0
0
0
clock_gen_sel_val
0
driver_strength_sel_val
0
8
0
0
4
0
0
0
0
0
0
0
0
1
sdclk_freq_sel_val
12
rsvd
15
August 2015
Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.6.36
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
1h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
High Speed Preset Values Register (PRESET_VALUE_2)—Offset
64h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_2: [BAR0] + 64h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
12
0
17.6.37
rsvd
0
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
0
0
0
0
4
0
0
0
0
0
0
0
0
0
sdclk_freq_sel_val
0
driver_strength_sel_val
0
8
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
0h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
SDR12 Preset Values Register (PRESET_VALUE_3)—Offset 66h
Access Method
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_3: [BAR0] + 66h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0001h
12
0
17.6.38
0
rsvd
0
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
0
0
0
4
0
0
0
0
0
0
0
0
1
sdclk_freq_sel_val
0
driver_strength_sel_val
0
8
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
1h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
SDR25 Preset Values Register (PRESET_VALUE_4)—Offset 68h
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_4: [BAR0] + 68h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
Intel® Quark™ SoC X1000
Datasheet
654
0
0
0
0
clock_gen_sel_val
0
driver_strength_sel_val
0
8
0
0
4
0
0
0
0
0
0
0
0
0
sdclk_freq_sel_val
12
rsvd
15
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Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
17.6.39
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
0h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
SDR50 Preset Values Register (PRESET_VALUE_5)—Offset 6Ah
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_5: [BAR0] + 6Ah
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
12
0
17.6.40
0
rsvd
0
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
0
0
0
4
0
0
0
0
0
0
0
0
0
sdclk_freq_sel_val
0
driver_strength_sel_val
0
8
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
0h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
SDR104 Preset Values Register (PRESET_VALUE_6)—Offset 6Ch
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_6: [BAR0] + 6Ch
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
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Default: 0000h
12
0
17.6.41
8
0
rsvd
0
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
0
0
0
4
0
0
0
0
0
0
0
0
0
sdclk_freq_sel_val
0
driver_strength_sel_val
0
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
0h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
DDR50 Preset Values Register (PRESET_VALUE_7)—Offset 6Eh
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
PRESET_VALUE_7: [BAR0] + 6Eh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
0
0
Bit
Range
Default &
Access
15: 14
00b
RO
13: 11
000b
RO
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0
rsvd
driver_strength_sel_val
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
sdclk_freq_sel_val
12
clock_gen_sel_val
15
Description
Reserved (driver_strength_sel_val): Reserved
Reserved (rsvd): Reserved
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Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
17.6.42
Default &
Access
Description
10
0b
RO
Clock Generator Select Value (clock_gen_sel_val): This bit is effective when Host
Controller supports programmable clock generator. 1 - Programmable Clock Generator,
0 - Host Controller Ver2.00 Compatible Clock Generator
9: 0
0h
RO
SDCLK Frequency Select Value (sdclk_freq_sel_val): 10-bit preset value to set
SDCLK Frequency Select in the Clock Control Register is described by a host system.
Boot Time-out control register (BOOT_TIMEOUT_CTRL)—Offset
70h
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
BOOT_TIMEOUT_CTRL: [BAR0] + 70h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
31
0
0
0
24
0
0
0
0
20
0
0
0
0
16
0
0
0
0
12
0
0
0
0
8
0
0
0
0
4
0
0
0
0
0
0
0
0
0
time_cnt_val
0
28
Bit
Range
31: 0
17.6.43
Default &
Access
Description
Boot Data Timeout Counter Value (time_cnt_val): This value determines the
interval by which DAT line time-outs are detected during boot operation for eMMC4.4
card. The value is in number of sd clock.
0h
RW
Debug Selection Register (DEBUG_SEL)—Offset 74h
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
DEBUG_SEL: [BAR0] + 74h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
4
0
0
0
0
rsvd
0
0
Bit
Range
Default &
Access
7: 1
00h
RO
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Document Number: 329676-005US
0
0
0
debug_sel
7
Description
Reserved (rsvd): Reserved
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Bit
Range
Default &
Access
17.6.44
Debug Select (debug_sel): 1- cmd register, Interrupt status, transmitter module,
ahb_iface module and clk sdcard signals are probed out.
0 - receiver module and fifo_ctrl module signals are probed out
0b
WO
0
Description
Shared Bus Control Register (SHARED_BUS)—Offset E0h
This register is optional. The devices on shared bus are not intended to be controlled by
the Standard Host Driver. This is because shared bus configuration depends on a host
system; the devices on shared bus may be controlled by a specific driver of a host
system.
Access Method
Type: Memory Mapped I/O Register
(Size: 32 bits)
SHARED_BUS: [BAR0] + E0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00000000h
Bit
Range
31
30: 24
23
22: 20
19
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0
0
0
0
0
Default &
Access
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
num_clk_pin
0
0
rsvd5
0
num_int_pin
0
4
rsvd4
0
8
bus_width
0
12
rsvd3
0
clk_pin
0
16
rsvd2
0
20
int_pin
0
24
pwr_ctrl
0
rsvd0
0
28
rsvd1
31
Description
0b
RO
Reserved (rsvd0): Reserved
0h
RW
Back-End Power Control (pwr_ctrl): Each bit of this field controls back-end power
supply for an embedded device. Host interface voltage (VDDH) is not controlled by this
field. The number of devices supported is specified by Number of Clock Pins and a
maximum of 7 devices can be controlled.
D16 Back-end Power Control for Device 1
D17 Back-end Power Control for Device 2
D18 Back-end Power Control for Device 3
D19 Back-end Power Control for Device 4
D20 Back-end Power Control for Device 5
D21 Back-end Power Control for Device 6
D22 Back-end Power Control for Device 7
The function of each bit is defined as follows:
0 Back-end Power is Off
1 Back-end Power is Supplied
Back-End power control is effective for embedded memory devices in the Sleep State
that support the Sleep command (CMD14) to reduce power consumption and embedded
SDIO devices when IOEx is set to 0.
0b
RO
Reserved (rsvd1): Reserved
0h
RW
Interrupt Pin Select (int_pin): Interrupt pin inputs are enabled by this field. Enable
of unsupported interrupt pin is meaningless.
000b - Interrupt is detected by Interrupt Cycle,
xx1b - INT_A is Enabled,
x1xb - INT_B is Enabled,
1xxb - INT_C is Enabled
0b
RO
Reserved (rsvd2): Reserved
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Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
0h
RW
Clock Pin Select (clk_pin): One of clock pin outputs is selected by this field. Select of
unsupported clock pin is meaningless. Refer to Figure 2-38 (An Example Timing of
Selecting Clock Pin) on SD Host Controller Simplified Specification Version 3.00 for the
timing of clock outputs.
000b - Clock Pins are Disabled,
001b - CLK[1] is Selected,
010b - CLK[2] is Selected
--111b - CLK[7] is Selected
0b
RO
Reserved (rsvd3): Reserved
14: 8
0h
RO
Bus Width Preset (bus_width): Shared bus supports mixing of 4-bit and 8- bit bus
width devices. Each bit of this field specifies the bus width for each embedded device.
The number of devices supported is specified by Number of Clock Pins and a maximum
of 7 devices are supported.This field is effective when multiple devices are connected to
a shared bus (Slot Type is set to 10b in the Capabilities register). In the other case,
Extended Data Transfer Width in the Host Control 1 register is used to select 8-bit bus
width. As use of 1-bit mode is not intended for shared bus, Data Transfer Width in the
Host Control 1 register should be set to 1. D08 - Bus width preset for Device 1, D09 Bus width preset for Device 2, D10 - Bus width preset for Device 3, D11 - Bus width
preset for Device 4, D12 - Bus width preset for Device 5, D13 - Bus width preset for
Device 6, D14 - Bus width preset for Device 7 The function of each bit is defined as
follows: 0 - 4 bit bus width mode, 1 - 8 bit bus width mode
7: 6
00b
RO
Reserved (rsvd4): Reserved
5: 4
0h
RO
Number of Interrupt Input Pins (num_int_pin): This field indicates support of
interrupt input pins for shared bus system.Three asynchronous interrupt pins are
defined, INT_A#, INT_B# and INT_C#. Which interrupt pin is used is determined by the
system. Each one is driven by open drain and then wired or connection is possible. 00b
- Interrupt Input Pin is Not Supported, 01b - INTA is Supported, 10b - INTA and INTB
are Supported, 11b - INTA, INTB and INTC are Supported
3
0b
RO
Reserved (rsvd5): Reserved
0h
RO
Number of Clock Pins (num_clk_pin): This field indicates support of clock pins to
select one of devices for shared bus system. Up to 7 clock pins can be supported.Shared
bus is supported by specific system. Then Standard Host Driver does not support control
of these clock pins. 000b - Shared bus is not supported, 001b - 1 SDCLK pin is
supported, 010b - 2 SDCLK pins are supported, ..... , 111b - 7 SDCLK pins are
supported
18: 16
15
2: 0
17.6.45
SPI Interrupt Support Register (SPI_INT_SUP)—Offset F0h
Access Method
Type: Memory Mapped I/O Register
(Size: 8 bits)
SPI_INT_SUP: [BAR0] + F0h
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 00h
7
4
0
0
0
0
0
0
0
0
spi_int_support
0
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
17.6.46
Bit
Range
Default &
Access
Description
7: 0
00h
RW
SPI Interrupt Support (spi_int_support): This bit is set to indicate the assertion of
interrupts in the SPI mode at any time, irrespective of the status of the card select (CS)
line. If this bit is zero, then SDIO card can only assert the interrupt line in the SPI mode
when the CS line is asserted.
NOTE: Not part of the SD Host Controller Simplified Specification Version 3.00
Slot Interrupt Status Register (SLOT_INT_STAT)—Offset FCh
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
SLOT_INT_STAT: [BAR0] + FCh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: 0000h
0
0
8
0
0
0
0
0
4
0
0
0
Bit
Range
Default &
Access
15: 8
7: 0
17.6.47
0
0
reserved
0
12
0
0
0
0
int_sig_slot
15
Description
00h
RO
Reserved (reserved): Reserved
00h
RO
Interrupt Signal For Each Slot (int_sig_slot): These status bit indicate the logical
OR of Interrupt signal and wake up signal for each slot. A maximum of 8 slots can be
defined. If one interrupt signal is associated with multiple slots. the HD can know which
interrupt is generated by reading these status bits. By a power on reset or by Software
Reset For All, the Interrupt signal shall be de asserted and this status shall read 00h. Bit
00 - Slot 1, Bit 01 - Slot 2, Bit 02 - Slot 3, ----- -----, Bit 07 - Slot 8
Host Controller Version Register (HOST_CTRL_VER)—Offset FEh
Access Method
Type: Memory Mapped I/O Register
(Size: 16 bits)
HOST_CTRL_VER: [BAR0] + FEh
BAR0 Type: PCI Configuration Register (Size: 32 bits)
BAR0 Reference: [B:0, D:20, F:0] + 10h
Default: A702h
0
1
8
0
0
vend_ver_num
1
12
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1
1
1
4
0
0
0
0
0
0
0
1
0
spec_ver_num
15
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Document Number: 329676-005US
SDIO/SD/eMMC—Intel® Quark™ SoC X1000
Bit
Range
Default &
Access
Description
15: 8
a7h
RO
Vendor Version Number (vend_ver_num): This status is reserved for the vendor
version number. The HD should not use this status.
7: 0
02h
RO
Specification Version Number (spec_ver_num): This status indicates the Host
Controller Spec. Version. The upper and lower 4- bits indicate the version. 00 - SD Host
Specification version 1.0, 01 - SD Host Specification version 2.00 including only the
feature of the Test Register, 02 - SD Host Specification Version 3.00, others - Reserved
§§
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Document Number: 329676-005US
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Intel® Quark™ SoC X1000—SDIO/SD/eMMC
Intel® Quark™ SoC X1000
Datasheet
662
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Document Number: 329676-005US
High Speed UART—Intel® Quark™ SoC X1000
18.0
High Speed UART
The Intel® Quark™ SoC X1000 implements two instances of a 16550 compliant UART
controller that supports baud rates between 300 and 2764800. Hardware flow control is
also supported.
Note:
Only one UART controller (UART0) provides MODEM pins.
18.1
Signal Descriptions
See Chapter 2.0, “Physical Interfaces” for additional details.
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction can be either input, output, or I/O (bidirectional)
• Type: The buffer type found in Chapter 4.0, “Electrical Characteristics”
• Description: A brief explanation of the signal’s function
Table 113.
UART 0 Interface Signals
Signal Name
Table 114.
Direction/
Type
Description
SIU0_RXD
I
UART 0 - Serial Input
SIU0_TXD
O
UART 0 - Serial Output
SIU0_RTS_B
O
UART 0 - MODEM Request to Send
SIU0_CTS_B
I
UART 0 - MODEM Clear to Send
SIU0_DCD_B
I
UART 0 - MODEM Data Carrier Detect
SIU0_DSR_B
I
UART 0 - MODEM Data Set Ready
SIU0_DTR_B
O
UART 0 - MODEM Data Terminal Ready
SIU0_RI_B
I
UART 0 - MODEM Ring Indicator
UART 1 Interface Signals
Signal Name
Direction/
Type
Description
SIU1_RXD
I
UART 1 - Serial Input
SIU1_TXD
O
UART 1 -Serial Output
SIU1_RTS_B
O
UART 1 - MODEM Request to Send
SIU1_CTS_B
I
UART 1 - MODEM Clear to Send
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Datasheet
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Intel® Quark™ SoC X1000—High Speed UART
18.2
Features
18.2.1
UART Function
The UART transmits and receives data in bit frames as shown in Figure 37.
• Each data frame is between 7 and 12 bits long, depending on the size of data
programmed and if parity and stop bits are enabled.
• The frame begins with a start bit that is represented by a high-to-low transition.
• Next, 5 to 8 bits of data are transmitted, beginning with the Least Significant Bit
(LSB). An optional parity bit follows, which is set if even parity is enabled and an
odd number of ones exist within the data byte; or, if odd parity is enabled and the
data byte contains an even number of ones.
• The data frame ends with one, one and a half, or two stop bits (as programmed by
users), which is represented by one or two successive bit periods of a logic one.
Figure 37.
UART Data Transfer Flow
Start
Bit
Data
[0]
Data
[1]
Data
[2]
Data
[3]
Data
[4]
Data
[5]
Data
[6]
Data
[7]
Parity
Bit
Stop
Bit 1
Stop
Bit 2
TXD or RXD pin
LSB
MSB
Shaded bits are optional that users can program.
18.2.2
Baud Rate Generator
The baud rates for the UARTs are generated from the base frequency (Fbase) indicated
in Table 115 by programming the DLH and DLL registers as divisor. The hexadecimal
value of the divisor is (IER_DLH[7:0]
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